Low Power Design/Methodology Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA is seeking a Low Power Design/Methodology Engineer in Tijuana, Baja California, Mexico. This role involves designing adaptive power management controllers, performing RTL design and verification, and supporting SoC integration. The ideal candidate will have a Bachelor's degree and 2+ years of ASIC design experience, with familiarity in low power techniques and scripting languages.

Responsibilities

Design adaptive power management controller, on-chip sensor controller and digital power meter.
Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks.
Work closely with technology/circuit design team to close IP block specification/requirement.
Work closely with verification/physical design team to complete the IP design implementation.
Support SoC team to integrate low power / power management IP solution into wireless SoC chips and front-end design flows.
Work closely with system/software/test team to enable the low power feature in wireless SoC product.
Work closely with system/software/test team to enable functional safety feature in automotive SoC product.
Create/Enhance low power methodologies covering entire design cycle from RTL to GDS.
Analyze how a new methodology will affect different phases of the design/verification cycle and work on fixing any issues.
Provide feedback for low-power chip and system architecture.
Understand and perform block & chip-level power analysis.
Understand and create block-level power models.
Collaborate closely with cross-function team to research, design and implement performance and power management strategy for product roadmap.

Requirements

Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field.
3 years of experience doing low power digital ASIC design.
Familiar with ASIC front-end design process and related flow, including u-arch, RTL coding, simulation, synthesis, STA.
Familiar with scripting languages like Python, Perl, TCL
Understanding of electrical engineering concepts, circuit analysis and logic design skills.

Desired Qualifications

Previous experience in AVS (adaptive voltage scaling) desired.
Familiarity with advanced low power techniques and tools such as UPF, CLP, power aware DV and high speed clocking desired.
Proficiency in Verilog/System Verilog coding, verification techniques, and scripting language, such as: Perl, Python, Tcl, and Make etc.
Good understanding of SoC architecture/micro-architecture.
Understanding of automotive functional safety standard ISO 26262 and analysis technique (FMEA/FMEDA) is a plus.
Strong debugging capabilities at simulation, emulation, and Silicon environments, including ability to design interesting debug experiments.

Benefits

Qualcomm is an equal opportunity employer.
Qualcomm is committed to providing an accessible process.
Qualcomm is committed to making our workplace accessible for individuals with disabilities.

Skills

RTLASIC designPythonPerlTclSystem VerilogUPFISO 26262

#ASIC#Low Power Design#Methodology

About Qualcomm

Enabling a world where everyone and everything can be intelligently connected.

Enabling a world where everyone and everything can be intelligently connected.\n\n

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Company

Qualcomm

Job Posted

1 day ago

Employment Type

Full Time

Work mode

On Site

Experience Level

Mid-Senior

Locations

Tijuana, Mexico

Qualification

Bachelor

Applicants

Be an early applicant

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