Layout Design, Staff Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Synopsys sucht einen Staff Engineer für Layout Design in Hyderabad, Telangana. Diese Vollzeitstelle konzentriert sich auf das Design und die Entwicklung modernster Halbleiterlösungen, insbesondere für DDR und HBM PHY IP in fortschrittlichen Prozesstechnologien. Die Rolle erfordert tiefgreifende Expertise in Custom Layout, Mentoring von Junior-Ingenieuren und die Zusammenarbeit mit interdisziplinären Teams zur Optimierung von Fläche, Leistung und Zuverlässigkeit.

Responsibilities

Lead layout development for next-generation DDR and HBM PHY IP across 7nm, 5nm, and below in FinFET and GAA process technologies
Own floorplanning, layout execution, and design reviews for critical analog and mixed-signal blocks within memory PHY subsystems
Drive layout quality through PERC, EMIR, DFM checks, LEF generation, and release readiness, ensuring designs meet foundry and customer specifications
Collaborate with circuit design, verification, and product engineering teams to resolve layout-related issues, optimize for area and performance, and meet project schedules
Mentor junior layout engineers on matching techniques, ESD and latch-up strategies, IO frame requirements, and deep submicron layout best practices
Estimate effort, plan schedules, and execute layout deliverables in cross-functional project settings with accountability for timelines and quality
Support customer-specific PHY requirements including bond-pad layout, pitch constraints, and custom IO configurations

Requirements

5+ years of hands-on custom layout experience, with demonstrated leadership on complex analog or mixed-signal IP projects
Deep expertise in layout for 7nm and below process nodes, including FinFET and GAA technologies, with strong understanding of deep submicron effects
Proficiency in layout matching techniques, ESD and latch-up design, PERC, EMIR analysis, DFM checks, and LEF generation
Experience with PHY-level IP development, including bond-pad layout, IO frame design, and customer pitch requirements
Proven ability to lead projects, estimate effort, plan schedules, and deliver high-quality layout on time in cross-functional settings
Bachelor's or Master's degree in Electronics Engineering, VLSI Design, or related field

Desired Qualifications

Experience with DDR, HBM, or high-speed memory interface IP is a strong plus

Benefits

Competitive salaries
Comprehensive medical and healthcare plans
ETO and FTO Programs for Time Away
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Retirement Plans

Skills

DDRHBMFinFETGAAESDEMIRDFMLEF

#engineering#layout design#staff engineer

About Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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