DFT - Senior Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Qualcomm is looking for a Senior Engineer specializing in ASIC/DFT in Hyderabad, India. The role involves defining, designing, optimizing, verifying, and implementing IP for world-class products, with a strong emphasis on Design For Testability concepts, ATPG, and related tools.

Responsibilities

Define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development.
Determine product execution path in collaboration with cross-functional groups.
Apply in-depth knowledge of DFT concepts.
Perform scan insertion, ATPG, coverage analysis, and transition delay test coverage analysis.
Define test mode timing constraints and provide timing fixes for violations.
Simulate test vectors.
Utilize knowledge of equivalence check and DFT DRC rules in RTL lint and ATPG tools.
Work in an international team and dynamic environment.
Adapt to new tools and methodologies.
Perform multi-tasking and work on several high-priority designs in parallel.
Problem solving, communication, and teamwork skills.

Requirements

Minimum of 3+ years experience in ASIC/DFT.
In-depth knowledge of DFT concepts.
In-depth knowledge and hands-on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis.
Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations.
Expertise in scripting languages such as perl, shell, etc.
Experience in simulating test vectors.
Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (Tessent, TK, TetraMax).
Excellent communication and team work skills and good English is required.

Desired Qualifications

Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field.
Working experience in Genus, Synopsys TetraMax/DFTMax and Cadence Encounter Test is a plus.
Ability to learn and adapt to new tools and methodologies.
Ability to do multi-tasking & work on several high priority designs in parallel.
Excellent problem solving skills.

Benefits

Qualcomm is an equal opportunity employer.
Commitment to providing an accessible process for individuals with disabilities.
Qualcomm is committed to making our workplace accessible for individuals with disabilities.

Skills

ASIC designASIC verificationASIC validationASIC integrationDFT conceptsscan insertionATPGcoverage analysisTransition delay test coverage analysistest mode timing constraintstiming fixesperlshell scriptingtest vectorsequivalence checkDFT DRC rulesRTL lintspyglassTessentTKTetraMaxGenusSynopsys TetraMaxDFTMaxCadence Encounter Test

#ASIC#DFT#Engineering#Technology#Chip Design#Semiconductor