Staff Digital Design Engineer GPU Hardware

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Qualcomm is seeking an experienced Staff Digital Design Engineer for its GPU Hardware Design team in Greece. The role involves technical leadership in the design and development of high-performance GPU hardware, from architecture to post-silicon support, using Verilog/SystemVerilog and AMBA protocols.

Responsibilities

Lead the design, implementation, integration, and delivery of complex synthesizable RTL for GPU and SoC hardware blocks.
Own technical solutions from requirements and microarchitecture through RTL release, integration, silicon bring-up, and debug.
Develop efficient and robust digital logic using Verilog and/or SystemVerilog.
Design and integrate interfaces based on AMBA protocols, including AXI and AHB.
Define and review block microarchitecture, interfaces, performance requirements, and implementation trade-offs.
Develop control logic, datapaths, register interfaces, arbiters, FIFOs, pipeline structures, and flow-control mechanisms.
Drive technical discussions and design reviews across architecture, verification, physical design, SoC, and software teams.
Provide technical leadership in debugging RTL simulation, lint, CDC, synthesis, timing, integration, and silicon issues.
Contribute to power, performance, and area optimization and ensure design decisions meet project objectives.
Establish and improve RTL design methodologies, coding standards, quality criteria, and development processes.
Mentor engineers and support the growth of the GPU digital design team.
Represent the design team in cross-functional planning, risk assessment, issue resolution, and execution tracking.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
10+ years of experience in digital design and RTL development for ASIC, SoC, or FPGA products.
Expertise in Verilog and/or SystemVerilog and strong knowledge of synthesizable RTL design practices.
Strong understanding of synchronous digital design, including finite-state machines, pipelining, clock-domain crossings, reset strategies, FIFO design, arbitration, flow control, and timing behavior.
Strong practical knowledge of AMBA protocols, particularly AXI and AHB.
Experience leading the implementation of complex hardware blocks and resolving design issues across multiple development phases.
Solid understanding of RTL simulation, debugging, synthesis, lint, CDC, timing analysis, and hardware implementation flows.
Ability to interpret architectural specifications and translate them into scalable, maintainable, and verifiable hardware implementations.
Strong technical leadership, communication, collaboration, and problem-solving skills.

Desired Qualifications

Understanding of memory controller designs is an added advantage.
Understanding of microprocessor architectures is an added advantage.
Experience designing hardware for GPUs, CPUs, multimedia, networking, storage, or other high-performance SoC subsystems.
Familiarity with GPU or accelerator architecture, memory systems, data movement, and performance considerations.
Experience with AXI interconnects, AHB-Lite interfaces, register interfaces, clock and reset controllers, and low-power design concepts.
Experience with scripting languages such as Python, Perl, or Tcl.
Familiarity with industry-standard EDA tools and ASIC development methodologies.
Track record of technical influence across teams and successful delivery of complex hardware projects.

Benefits

The opportunity to lead the development of advanced GPU hardware technologies.
Exposure to the complete ASIC development lifecycle.
Collaboration with experienced architects, designers, verification engineers, physical design engineers, and system teams.
A technically challenging and collaborative international engineering environment.
Opportunities for professional growth, technical leadership, and career development.
The chance to make a significant impact on Qualcomm GPU products and engineering processes.
competitive annual discretionary bonus program
opportunity for annual RSU grants
highly competitive benefits package