St Staff Engineer, Power Delivery

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Qualcomm is seeking a Staff Engineer to lead On-Chip Power Delivery Network (PDN) architecture for high-performance SoCs. You will define and optimize power-grid strategies, drive PDN-aware floorplanning, and establish budgets for IR drop, voltage droop, and electromigration. This role requires close collaboration with various engineering teams to ensure robust power delivery solutions across advanced technology nodes.

Responsibilities

Own on-chip power delivery network architecture and power-grid strategy for advanced-node, high-performance SoCs.
Define and optimize power-grid topology, rail structure, power domains, grid architecture, and power/ground distribution for critical IPs.
Drive PDN-aware floorplanning in collaboration with SoC Physical Design and IP teams.
Define and optimize on-die power-grid connectivity to bump interfaces.
Define and optimize the on-die decoupling-capacitance strategy.
Establish static IR-drop, dynamic voltage-droop, impedance, EM/current-density, and reliability budgets.
Perform and drive static IR, dynamic voltage-drop, transient, impedance, EM, and PDN coupling analyses.
Co-optimize the on-chip power grid with floorplan, timing, PPA, routing resources, bump allocation, and package connectivity.
Define the on-chip PG roadmap for advanced technology nodes, including evaluation of backside power delivery.
Drive PGPOR roadmap and architecture tradeoff analysis.
Partner closely with Physical Design, SoC Architecture, IP Design, Package/PI, and technology teams.
Develop scalable PDN extraction, modeling, simulation, signoff, and correlation methodologies.

Requirements

Master's or Ph.D. degree in Electrical Engineering, Computer Engineering, or related field with a focus on power integrity, VLSI, physical design, or semiconductor power delivery.
Deep expertise in on-chip power-grid architecture, PDN optimization, and advanced-node power delivery.
Experience with Cadence Voltus, Sigrity PowerSI, Ansys HFSS/Q3D/SiWave, HSpice, ADS, or equivalent power-integrity and circuit-simulation tools.
Experience developing or improving PDN extraction, modeling, analysis, automation, and signoff methodologies.
Knowledge of advanced power-grid technologies, backside power delivery, advanced packaging, and die-to-package power-delivery co-optimization.
Strong scripting and automation skills using Python, TCL, or similar languages.
Demonstrated ability to work cross-functionally with SoC Architecture, Physical Design, IP, Package, PI, and technology teams.

Benefits

Competitive annual discretionary bonus program.
Opportunity for annual RSU grants.
Highly competitive benefits package designed to support your success at work, at home, and at play.
Qualcomm is committed to providing an accessible process for individuals with disabilities.
Qualcomm is committed to making our workplace accessible for individuals with disabilities.

Skills

PythonTCLCadence VoltusSigrity PowerSIAnsys HFSSAnsys Q3DAnsys SiWaveHSpiceADS

#Power Delivery Network#On-Chip Power Delivery#Power-Grid Architecture#SoC#PDN#IR Drop#Dynamic Voltage Droop#Electromigration#Physical Design#Floorplanning