SoC Constraints Design Engineer, Silicon

Technology, Data & Digital · Software & Web Development · Embedded Systems · Software Engineering

In short

Du blir en del av Googles Silicon-team och utvecklar anpassade kiselösningar för Googles direkt- till konsumentprodukter. Du kommer att driva utvecklingen och valideringen av designbegränsningar, arbeta med sign-off-tidsmässig konvergens och samarbeta med implementeringsteam för att uppnå tidsmålen.

Responsibilities

Collaborate with Architecture/Microarchitecture/Register-Transfer Level (RTL) design teams to capture timing intent, and drive timing convergence.
Lead the development and validation of Synopsys Design Constraints (SDC) for complex System on a Chip (SoC) subsystems and top-level integration from architecture/microarchitecture documents that gets used in static timing analysis as well as physical design implementation.
Understand clocking structures and Clock Domain Crossing (CDC) strategies to ensure robust timing across all functional and test modes.
Design constraints validation across multiple corners/modes using Fishtail/Timevision.
Work closely with the design team and block owners throughout the project for sign-off timing convergence. Constraints promotion and demotion flow using fishtail, timevision.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with digital logic design principles, RTL design concepts.
1 year of experience with Static Timing Analysis, Constraints development and its validation, sign-off corner definitions, process margining, and setup of frequency goals with technology scaling and Process Design Kit (PDK) changes.
Experience with scripting languages (e.g., Python, Perl, Tcl) to automate workflows, parse electronic design automation (EDA) reports, and develop custom utilities.

Desired Qualifications

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
Experience in developing constraints and validating the same using Timing Constraints Manager (e.g., Synopsys)/TimeVision (e.g., Ausdia).
Experience with liberty timing models and Static Timing Analysis tools (e.g., TCM/Timevision, Primetime, Tempus).
Understanding of SoC Architecture, memory hierarchy, coherency, fabric interconnect protocols, clocking, and power management.
Understanding of various external Input/Output (IO) protocols.

Benefits

Google is proud to be an equal opportunity and affirmative action employer.

Skills

PythonPerlTclRTLSynopsys Design ConstraintsStatic Timing Analysis

#SoC#Silicon#Design Engineer#Digital Logic Design#RTL Design#Static Timing Analysis#Constraints Development#EDA#Python#Perl#Tcl#Google

About Google

Innovative Full-Stack Developer | Building Scalable Solutions with Node.js & React

At Google, our mission is to organize the world's information and make it universally accessible and useful. From Search to AI, we develop products and services that improve the lives of billions, empowering individuals and businesses globally. We're driven by a passion for innovation, a commitment to solving complex problems, and a belief in the transformative power of technology. Since our founding in 1998, we've remained dedicated to creating a more helpful and connected world.

See all open jobs at Google Read more about Google Website