NPU Design Verification Sr Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Qualcomm seeks an experienced NPU Design Verification Sr Engineer in Bangalore, India, to drive the verification of complex DSP/NPU IP. Responsibilities include implementing and improving System Verilog/UVM Testbench Architecture, developing new verification methodologies, and ensuring high-quality commercial success of products through hands-on simulation and debugging.

Responsibilities

Drive design verification of DSP IP by working with a global DSP design team.
Implement and improve System Verilog/UVM Testbench Architecture.
Develop and deploy new verification methodologies and automation.
Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals.
Perform hands-on simulations and debug IP, Subsystem, and SoC level fails and bugs.
Complete all required verification activities at IP level.
Utilize assertions, simulation, formal verification, HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, and emulation.
Responsible for gate level simulation bring-up and verification with timing simulations.
Responsible for power aware RTL verification and gate level simulation.

Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
2+ years experience in processor/ASIC design verification.
Solid background and understanding of Digital Design, Processor Architecture, Processor Verification, and Power aware verification.
Expertise in System Verilog Testbench Architecture and implementation.
Experience with advanced verification techniques such as formal and assertions.
Gate-Level Simulation and Debug — 0-delay, timing annotated and power aware.
Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence.
Scripting/Automation Skills — Perl, Python, Shell, Make file TCI.
Solid analytical and debugging skills.
Strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts.
Excellent inter-personal and communication skills.

Desired Qualifications

Experience in writing C based and assembly level testcases is preferred.
Exposure to power aware implementation and verification using UPF is a plus.
Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC is preferred.
Experience in Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred.
Experience in verification of Processor subsystems is preferred.
Experience in creating validation suite and building automation.

Benefits

Qualcomm is an equal opportunity employer.
Qualcomm is committed to providing an accessible process for individuals with disabilities.
Qualcomm is committed to making our workplace accessible for individuals with disabilities.