FY27 Intern - RF/Analog Verification Engineering Internship - Canada (4 or 16 months)

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Qualcomm is looking for an RF/Analog Verification Engineering Intern for their FY27 program in Markham, Canada. The role involves assisting in the pre-silicon verification of RFICs and developing an AI-driven verification framework to analyze calibration architectures and generate testbench scenarios. This internship offers a chance to work on cutting-edge technology and gain valuable experience in a global company.

Responsibilities

Write behavioral Systems Verilog models of analog blocks.
Develop and maintain functional verification plans/coverages.
Writing functional verification tests for block level and radio chip level.
Developing and debugging behavioral models for event driven simulation.
Verifying functionality of radio chip level.
Diagnose radio chip level functional symptoms.
Diagnosing failed tests.
Tracking results, and logging bugs.

Requirements

BSEE’s or BSCS’ candidate with focus in VLSI digital and/or RFA design courses
Application of Machine Learning algorithms
In study towards a bachelor’s, master's, or PhD degree in one of the following: Electrical Engineering, Computer Engineering, Engineering Science, Computer Science, or related field
Expected graduation date of November 2027 or later.
1+ years of academic experience with programming languages such as C, C++, Python, etc

Desired Qualifications

Master’s or PhD‘s candidate in EE, ECE, CE, or CS or equivalent
Experience with System Verilog, UVM, testbench generation, assertions, functional coverage, stimulus generation.
Knowledge of WIFI/GPS/RF transceiver architectures, phase lock loops (PLLs), analog-to-digital converters, and digital-to-analog converters (ADCs and DACs) would be extremely helpful.
Proficient at scripting and program development (Python, PyTorch, TensorFlow, scikit-learn, pandas, NumPy, RAG, C++, …).
Digital design or RFA design experience.
Modeling and verification experience.
Familiarity with SystemVerilog and methodologies like UVM are a plus.