DFT Engineering Director

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. The Digital ASIC Design Team is currently seeking candidates who will be responsible for the implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power, multi voltage designs.

Responsibilities

Implementation and verification of advanced DFT/DFD techniques for low power, multi voltage designs.
Deployment of DFT methodologies that reduce test cost, increase product quality, and enhance yield learning on leading edge process technologies.
DFT pattern generation, coverage analysis and debug.
Running and debugging gate level simulations.

Requirements

Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Solid hands-on experience with industry standard DFT techniques such as scan and MBIST.
Experience in both pre, and post-silicon in the DFT domain.

Desired Qualifications

15+ years industry experience in the implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power and multi voltage domain designs.
A strong fundamental knowledge of DFT is required.
Understanding of core-based test methodology and scan isolation.
Knowledge of various fault models such as Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and Cell Aware.
Knowledge in JTAG, Scan Compression, ATPG, Fault Simulation and at-speed testing.
Experience with industry EDA ATPG and insertion tools.
Experience in DFT implementation, Scan/ATPG, MBIST insertion/validation, coverage analysis.

Benefits

Competitive annual discretionary bonus program.
Opportunity for annual RSU grants.
Highly competitive benefits package designed to support your success at work, at home, and at play.
Qualcomm is committed to providing an accessible process for individuals with disabilities during the application/hiring process.
Qualcomm is committed to making our workplace accessible for individuals with disabilities.

Skills

ASICDFTScanMBISTJTAGATPGFault Simulation

#ASIC#DFT#DFD#low power#multi voltage#test cost#product quality#yield learning#process technologies#scan#MBIST#DFT pattern generation#coverage analysis#gate level simulations#pre-silicon#post-silicon#core-based test methodology#scan isolation#fault models#Stuck-at#Transition#Path Delay#Gate-Exhaustive#IDDQ#Cell Aware#JTAG#Scan Compression#ATPG#Fault Simulation#at-speed testing#EDA ATPG tools#insertion tools#Scan/ATPG#MBIST insertion/validation#coverage analysis