DDRSS Systems Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems · QA & Testing

In short

As a DDRSS Systems Engineer at Qualcomm, you will be responsible for validating, tuning, and optimizing the DDR subsystem. This role requires close collaboration with various teams to ensure power, performance, reliability, and functionality features are enabled. You will develop and validate low-level DDR subsystem firmware and APIs, analyze system issues, and contribute to next-generation memory subsystem capabilities.

Responsibilities

Develop and maintain low-level firmware and system APIs for DDR subsystem initialization, training, power management, and performance features.
Validate firmware functionality in simulation, emulation, FPGA, and silicon environments.
Analyze and debug system issues spanning hardware, firmware, and software domains.
Collect and interpret stability, performance, power, and reliability data to guide design and product decisions.
Collaborate across design, DV, software, architecture, and product teams to enable and optimize DDR features.
Perform DDR subsystem bring-up and characterization on pre-silicon and post-silicon platforms.
Debug memory subsystem issues involving LPDDR interfaces, caches, interconnects, and memory controllers.
Contribute to the definition and validation of next-generation memory subsystem capabilities and optimizations.

Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with a focus on Embedded Systems, Computer Architecture, or VLSI.
2+ years of experience in embedded firmware or low-level software development.
Strong programming skills in C.
Experience with embedded system debugging and hardware/software integration.
Understanding of digital design fundamentals and computer architecture concepts.
Experience using lab equipment and silicon debugging tools to collect and analyze system data.
Familiarity with LPDDR memory interface concepts and protocol fundamentals.

Desired Qualifications

Experience with LPDDR4/LPDDR5/LPDDR5X memory protocols, training algorithms, timing parameters, and power management features.
Experience with DDR subsystem validation, characterization, and post-silicon bring-up.
Experience debugging and collecting data from silicon platforms.
Experience developing or maintaining Verilog/SystemVerilog simulation testbenches and validation environments.
Familiarity with memory controllers, caches, coherent interconnects, and SoC architecture.
Experience in performance analysis, power optimization, or system tuning activities.
Familiarity with emulation platforms and FPGA prototyping environments.
Experience with Python, scripting, or automation used for validation and data analysis.

Benefits

Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package designed to support your success at work, at home, and at play