CPU Physical Design Engineer, Staff

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Qualcomm India Private Limited is seeking a Staff CPU Physical Design Engineer for their Snapdragon CPU team in Hyderabad. The role involves owning block-level physical design implementation from RTL to GDSII, including PnR, timing closure, power optimization, and physical verification, with a focus on advanced-node designs for mobile, compute, and IoT products.

Responsibilities

Own and drive block-level physical design implementation from RTL/netlist to GDSII.
Perform Place & Route (PnR), timing closure, power optimization, physical verification, and signoff activities.
Develop and optimize implementation methodologies, flows, and recipes to achieve best-in-class Performance, Power, and Area (PPA).
Create and execute design experiments to evaluate implementation strategies and drive QoR improvements.
Analyze, compare, and track implementation metrics to guide project decisions.
Collaborate closely with RTL Design, Synthesis, STA, Power, Thermal, and Verification teams to achieve aggressive PPA goals.
Debug and resolve implementation challenges related to timing, power, congestion, and physical verification.
Contribute to methodology improvements, automation, and flow enhancement using scripting.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
7+ years of experience in ASIC Physical Design and high-performance CPU implementation.
Strong experience in RTL-to-GDSII implementation flow.

Desired Qualifications

Extensive hands-on experience with Place & Route using Cadence Innovus and/or Synopsys Fusion Compiler.
Strong understanding of complete ASIC implementation flow, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, timing closure, physical verification, and signoff.
Experience with STA and timing signoff using PrimeTime and/or Tempus.
Expertise in SDC constraint generation, validation, and debugging.
Experience with multi-power domain designs and UPF/CPF implementation.
Good understanding of low-power design and implementation techniques.
Knowledge of formal verification tools such as Formality and/or Conformal.
Familiarity with IR/EM analysis, signal integrity, and power analysis.
Strong scripting skills in Tcl, Perl, and/or Python.
Experience working on advanced technology nodes (7nm and below preferred).
Understanding of CPU microarchitecture and critical timing paths.
Experience implementing high-frequency, high-performance CPU designs.
Strong knowledge of clock architecture and CTS methodologies for high-speed designs.
Exposure to constraint management tools and Verilog coding.
Excellent debugging, problem-solving, and communication skills.

Skills

RTLGDSIIPlace & Routetiming closurepower optimizationphysical verificationPPA optimizationCadence InnovusSynopsys Fusion CompilerFloorplanningPlacementCTSRoutingPrimeTimeTempusSDCUPFCPFIR/EM analysissignal integritypower analysisTclPerlPythonVerilog

#ASIC#Physical Design#CPU#SoC#RTL#GDSII#PnR#PPA#timing closure#STA#Cadence#Synopsys#advanced nodes