Circuit Analysis and Modeling Engineer, Senior - Cork, Ireland

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

As a Senior Circuit Analysis and Modeling Engineer in Cork, Ireland, you will drive the development and verification of models for custom memory IP within Qualcomm's CPU portfolio. This role involves deep collaboration with design, architecture, verification, and CAD teams to ensure accurate memory models and advanced CPU designs. The ideal candidate is a highly motivated and technically curious individual passionate about solving complex engineering challenges.

Responsibilities

Develop and maintain functional, behavioral, and performance models for custom memory IP.
Create DFT models for custom memories and collaborate with DFT engineers to define test architectures and memory test interfaces.
Partner with verification teams to develop verification strategies and ensure comprehensive coverage of memory functionality in SoC environments.
Collaborate with architecture teams to define, evaluate, and model next-generation CPU memories.
Perform characterization, timing, power, and performance analysis for critical memory blocks.
Define and maintain verification methodologies, quality metrics, and release criteria for memory models and collateral.
Work with CAD teams to develop and enhance automation for model generation, validation, release, and analysis flows.
Collaborate with circuit designers to optimize memory designs for performance, power, area, yield, and testability.
Drive continuous improvements in modeling quality, automation, and development efficiency across the memory organization.

Requirements

Masters Degree in Electrical Engineering, Computer Engineering, or a related field OR Bachelors degree in one of those fields with 2+ years of industry experience.
Experience developing functional and behavioral models for custom IP and memory macros.
Expertise in one or more of the following areas: SRAM circuit design, Functional verification, Static timing analysis, Computer architecture.
Proficiency in Python, Perl, Tcl, shell scripting, or similar languages for automation and flow development.
Experience with industry-standard custom design, verification, and analysis tools.
Strong problem-solving skills and ability to collaborate effectively across multiple engineering disciplines.
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.

Desired Qualifications

Master's degree in Electrical Engineering or Computer Engineering.
Experience with Verilog, SystemVerilog, UVM, and assertion-based verification methodologies.
Knowledge of memory redundancy, repair algorithms, and memory test methodologies.
Knowledge of DFT concepts and industry-standard tools such as Tessent, Tetramax, and Synopsys SMS.
Experience developing automation frameworks, release flows, or modeling infrastructure.
Familiarity with low-power design, timing closure, and memory characterization methodologies.

Benefits

Salary, stock and performance related bonus
Maternity/Paternity Leave
Employee stock purchase scheme
Matching pension scheme
Education Assistance
Relocation and immigration support (if needed)
Life, Medical, Income and Travel Insurance
Subsidised memberships for physical and mental well-being
Bicycle purchase scheme
Employee run clubs, including, running, football, chess, badminton + many more

Skills

PythonPerlTclVerilogSystemVerilogUVM

#CPU#Memory IP#Circuit Analysis#Modeling#DFT#Verification#CAD Automation#SRAM#Functional Verification#Static Timing Analysis#Computer Architecture#Python#Perl#Tcl#Shell Scripting#Verilog#SystemVerilog#UVM#Low-power design#Timing Closure#Memory Characterization#Automation Frameworks