Camera Subsystem Integration Lead

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Als erfahrener ASIC-Design- und Subsystem-Integrationsingenieur führen Sie die Integration von Kamera- und Bildverarbeitungs-Subsystemen in zukünftige SoCs an. Ihre Verantwortung umfasst die technische Führung, die RTL-Integration, die Zusammenarbeit mit verschiedenen Teams und die Behebung komplexer technischer Probleme in einem schnelllebigen Umfeld.

Responsibilities

Own and drive Camera subsystem-level RTL integration across multiple Camera and Image Processing IPs.
Collaborate with hardware and system architects to define subsystem architecture, interfaces, and integration requirements.
Lead integration of new IPs, features, and SoC-facing interfaces.
Own top-level integration of clocks, resets, power domains, registers/address maps, interrupts, buses/interconnects, and configuration paths.
Drive RTL baseline, integration, and release readiness for key project milestones.
Run and review RTL quality checks including lint, CDC/RDC, low-power checks, connectivity checks, synthesis, and timing analysis.
Evaluate performance, power, area, scalability, and implementation tradeoffs.
Partner with DV teams to define subsystem-level verification requirements and integration test scenarios.
Lead debug of complex issues spanning multiple IPs and subsystem/SoC boundaries.
Identify integration risks early and drive cross-functional technical issues to closure.
Drive integration methodology and automation improvements to improve quality and execution efficiency.
Provide technical guidance and mentorship to engineers across the Camera HW team.

Requirements

10+ years of industry experience in ASIC/SoC design and integration.
Verilog/SystemVerilog RTL design and debugging.
Complex ASIC/SoC subsystem integration.
Design Verification and subsystem-level verification methodologies.
SoC bus/interconnect protocols such as AHB and AXI.
Clock, reset, interrupt, register, and power-domain integration.
RTL quality methodologies including lint, CDC/RDC, synthesis, timing analysis, and low-power checks.
Experience working across Design, DV, Architecture, Physical Design, Software, and SoC teams.
Technical leadership, communication, problem-solving, planning, and execution skills.

Desired Qualifications

Experience with Camera, Image Processing, Video, Multimedia, Graphics, or DSP hardware.
Experience with ASIC implementation and integration of Camera/Image Processing IP.
Understanding of high-bandwidth data paths, memory systems, NoC/interconnects, and performance optimization.
Experience with low-power methodologies and UPF-based flows.
Experience with Python, Perl, Tcl, or similar scripting languages for automation.
Experience taking complex ASIC subsystems from architecture and RTL through verification, SoC integration, tapeout, and silicon bring-up.

Benefits

Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package designed to support your success at work, at home, and at play.
More details about our US benefits available via a link.

Skills

VerilogSystemVerilogAHBAXIlintCDC/RDCsynthesistiming analysislow-power checksPythonPerlTcl

#Camera Engineering#ASIC Design#Subsystem Integration#SoC#RTL Integration#Hardware Engineering#Systems Engineering#DV#Physical Design#Software#Power Management#Verilog#SystemVerilog#AHB#AXI#Lint#CDC/RDC#Synthesis#Timing Analysis#Low-Power Checks#Python#Perl#Tcl