ASICS Design Verification Engineer-Senior to Staff

Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing

In short

Qualcomm seeks a Senior to Staff ASICS Design Verification Engineer for their San Diego, California office. This role involves comprehensive pre-silicon test planning, testbench development using SystemVerilog-UVM, coverage development, and formal verification. Experience with power-aware UPF verification flows and automation for efficiency is also required.

Responsibilities

Lead the complete verification lifecycle, from system-level concept to tape out and post-silicon support.
Perform comprehensive pre-silicon test planning for digital power IP's.
Develop testbenches using advanced verification methodologies such as SystemVerilog-UVM.
Develop coverage models and assertion models.
Conduct formal verification, including property checking.
Learn and deploy power-aware UPF verification flow and methodology.
Involve in developing automation to improve verification efficiency.

Requirements

Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field.
2+ years of experience with ASIC design and verification tools, techniques, and methodology.

Desired Qualifications

Master’s degree in Computer Science, Electrical Engineer, Computer Engineering, or a closely related field
6+ years of experience with ASIC design and verification tools, techniques, and methodology
6+ years of experience with digital design concepts and RTL languages such as SystemVerilog or Verilog, or VHDL.
6+ years of experience with computer architecture fundamentals, Object-oriented programming concepts and C or C++ programming skills.
6+ years of experience with developing block-level testbench environment using SystemVerilog
6+ years of experience with verification methodologies through coursework or past experiences such as UVM or OVM and exposure to Assertion based Formal Verification
6+ years of experience with scripting/automation skills using either Perl or python
Experience with AMBA Bus protocol (AXI/AHB/APB etc) is desirable
Knowledge or experience with Assertion Based Formal Verification is desirable

Benefits

Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package designed to support your success at work, at home, and at play
Reasonable accommodations for individuals with disabilities during the application/hiring process