ASIC Digital Design, Sr Staff Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing

In short

Synopsys seeks a Sr Staff Engineer for ASIC Digital Design in Hyderabad, India. This role focuses on end-to-end verification of high-speed protocols (UCIe, PCIe, DDR) using UVM and SystemVerilog. The ideal candidate has 7+ years of experience, excels at debugging complex issues, and can translate protocol specs into test plans and coverage models.

Responsibilities

Own end-to-end verification of UCIe, PCIe, or DDR IP blocks, from test planning and environment bring-up through coverage closure and sign-off
Build and extend UVM testbenches in SystemVerilog, including agents, sequencers, scoreboards, coverage models, and protocol checkers
Write directed and constrained-random tests that stress protocol compliance, corner cases, and multi-layer interactions
Debug complex RTL and testbench failures using Synopsys Verdi, including waveform analysis, protocol trace, and transaction-level debug
Translate protocol specifications into executable test plans, assertions (SVA), and functional coverage models that map to real silicon risk
Collaborate with design, architecture, and silicon validation teams on bug triage, ECO impact analysis, and bring-up readiness
Mentor verification engineers on UVM methodology, debug techniques, and protocol understanding, and contribute to design and verification reviews

Requirements

7+ years of hands-on ASIC or SoC design verification experience, with at least 3 years on protocol-heavy IP
Deep working knowledge of at least one high-speed protocol: PCIe, UCIe, or DDR, with the ability to read specs and build compliant testbenches
Strong UVM methodology experience, including building agents, writing constrained-random sequences, implementing scoreboards, and closing functional coverage
Solid SystemVerilog skills, including object-oriented programming, constrained-random stimulus generation, and SystemVerilog Assertions (SVA)
Proven ability to debug complex failures using Synopsys Verdi or equivalent tools (FSDB, protocol analyzers, transaction-level debug)
Experience with industry simulators such as VCS, Xcelium, or Questa, and familiarity with regression and coverage tools like URG
B.Tech or M.Tech in Electronics, VLSI, Electrical Engineering, or related discipline

Desired Qualifications

Working knowledge of a second protocol (PCIe, UCIe, DDR, CXL) is a strong plus

Benefits

Competitive salaries
Comprehensive medical and healthcare plans
ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Retirement plans that vary by region and country

Skills

SystemVerilogUVMPCIeUCIeDDRSVAVerdiVCSXceliumQuestaURGCXL

#ASIC#Digital Design#Sr Staff Engineer#Engineering#Semiconductor#IP Verification#SystemVerilog#UVM#PCIe#UCIe#DDR#SVA#Verdi

About Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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