ASIC Digital Design, Sr Manager-18730

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Synopsys is seeking a Sr. Manager for ASIC Digital Design in Mississauga, Ontario, to lead teams in developing next-generation SERDES PHY IP solutions. This role requires a visionary technical leader with expertise in Verilog, System Verilog, and front-end design flows, as well as people management experience, to drive innovation and deliver industry-leading semiconductor products.

Responsibilities

Leading a diverse team of design engineers in the development of next-generation SERDES PHY IP solutions.
Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.
Planning, scheduling and driving all phases of SERDES PHY IP design, from specification through productization and customer support.
Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles.
Mentoring and developing team members, fostering technical growth, and a culture of innovation.
Engaging customers, providing support for successful IP integration into their SoCs, and addressing technical challenges.

Requirements

Bachelor’s degree or higher in Electrical Engineering, with 15 +years of complex technical development experience.
Minimum 2 years’ experience in people management and employee development.
Proficiency in modeling, synthesizable Verilog and System Verilog design concepts and implementation.
Strong background in front-end design flows: Linting, synthesis, static timing analysis (STA), CDC/RDC, DFT, and power optimization.
Excellent communication skills and the ability to work independently and collaboratively.

Desired Qualifications

Understanding the PCIe and Ethernet standard is a plus.
Self-starter independent leader who thrives in a fast-paced, innovative setting and can drive task still closure.
Strong problem-solver with a strategic, analytical mindset.
Inspirational leader who motivates and develops technical talent.
Collaborative team players who excels in cross-functional environments.
Effective communicator who can translate complex technical concepts to diverse audiences.

Benefits

Competitive salaries ($166,000-$248,000).
Comprehensive medical and healthcare plans.
ETO and FTO Programs for time away.
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
ESPP: Purchase Synopsys common stock at a 15% discount.
Retirement Plans (vary by region and country).

Skills

VerilogSystem VerilogLintingSynthesisStatic Timing AnalysisPower OptimizationSERDESPHYPCIeEthernet

#ASIC#Digital Design#Sr Manager#Engineering#Hardware Engineers#Semiconductor#Chip Design#IP Integration#SERDES PHY IP#Verilog#System Verilog#Front-end flows#Linting#Synthesis#Static Timing Analysis#Power Optimization#PCle#Ethernet

About Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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