Applications Engineering, Staff Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Synopsys is seeking a Staff Engineer in Applications Engineering to drive innovations in chip design and verification. The role involves collaborating with R&D and customers on hardware-assisted verification products, defining test strategies, and becoming an expert in emulation and prototyping methodologies. This position requires a BSEE/MS with 10+ years of experience and proficiency in Verilog, System Verilog, VHDL, and scripting languages.

Responsibilities

Collaborating closely with R&D and customers on hardware-assisted verification products.
Driving all aspects of the technology life cycle, from development to product sign-off and customer deployment.
Defining test strategies and methodologies to improve ease-of-use, quality of results, and interoperability with other Synopsys tools.
Becoming an expert in emulation and prototyping methodologies and flows, including design, partitioning, testing, synthesis, and simulation-based verification.
Leveraging close interaction with customers, R&D, Marketing, and Sales teams to demonstrate the differentiated emulation/verification environment.
Adapting to recognized best practices and policies in Synopsys to become proficient in various processes involved in the Product Release Cycle.
Working with designs from varied verticals to enable and support key ZeBu products in early-stage development.

Requirements

BSEE/MS with 10+ years of related experience.
Expertise in Emulation and/or Prototyping flows, systems, and methodologies.
Strong proficiency in Verilog, System Verilog, VHDL and C/C++
Understanding of verification concepts and experience with functional simulators.
Experience with scripting languages like Python and Tcl
Knowledge in Simulation flows, Assertion, DPI, and Transactors.
Complex problem-solving and debugging skills.
Strong communication skills and the ability to interact with customers and peers.

Desired Qualifications

Knowledge in synthesis and timing analysis concepts (preferred).
Familiarity with Synopsys solutions and tools like ZeBu, HAPS, VCS, Verdi, Proto Compiler, Synplify, DC, and Formality (preferred).
Experience with Xilinx & Altera architecture and toolchains (preferred).
Protocols like PCIe, USB, Ethernet, DRAMs, HBM, NAND Flash (preferred).
Computing systems like CPU architecture, OS (preferred)
Understanding of SW/HW debug methodologies and experience with standard SW/HW debug tools (preferred).
DFT solutions (preferred)

Benefits

Comprehensive range of health, wellness, and financial benefits.
Total rewards include both monetary and non-monetary offerings.

Skills

VerilogSystem VerilogVHDLPythonTclC/C++

#hardware-assisted verification#emulation#prototyping#design#partitioning#testing#synthesis#simulation-based verification#HPC#AI#storage#networking#automotive

About Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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