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Staff Engineer, Physical Design/Implementation

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I korthet

Staff Engineer for Physical Design/Implementation at Qualcomm in Toronto, Canada. This role leads and executes end-to-end physical design for complex ASIC products in advanced technology nodes, focusing on power, performance, and area (PPA) targets. Requires strong technical leadership and collaboration with cross-functional teams for silicon tapeouts.

Ansvarsområden

  • Lead and execute end-to-end Physical Design flow for SoC and retimer ASICs, including Floorplanning, Clock Tree Synthesis (CTS), Placement & Routing, Power Delivery Network (PDN), and Timing analysis and closure.
  • Plan and implement full-chip or hierarchical designs, including full-reticle-scale integration.
  • Drive timing closure across all corners and modes (MMMC), including SI-aware optimization.
  • Perform and review physical verification checks: DRC, LVS, DFM, DFY.
  • Collaborate with cross-functional engineering teams (front-end, analog/SerDes, DFT, packaging, silicon validation) to ensure design convergence and tapeout readiness.
  • Lead integration of high-speed SerDes macros and mixed-signal IP, ensuring robust floorplan and signal integrity alignment.
  • Drive IR/EM closure, power optimization, and congestion mitigation for large die designs.
  • Provide schedules, risk assessment, and execution tracking to drive successful silicon tapeouts.
  • Act as a strong technical contributor in design reviews and project meetings, influencing architecture and implementation decisions.
  • Develop and improve physical design methodologies and flows to enhance efficiency and scalability.

Krav

  • Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of experience, OR Bachelor’s degree and 4+ years of progressive experience in ASIC Physical Design or related domain.
  • Strong experience with end-to-end ASIC Physical Design flow.
  • Strong experience with Timing closure and signoff methodologies.
  • Strong experience with Physical verification flows.
  • Hands-on expertise in industry-standard EDA tools (e.g., Cadence Innovus / Synopsys ICC2).
  • Solid understanding of Power delivery and reliability (IR/EM).
  • Solid understanding of Clocking architectures and CTS.
  • Solid understanding of Large-scale SoC integration challenges.

Önskade kvalifikationer

  • Experience with high-speed SerDes / retimer designs (PAM4-class signaling).
  • Experience with full-reticle or near-reticle SoC implementation.
  • Familiarity with multi-die / chiplet / advanced packaging architectures.
  • Exposure to data center, networking, or optical connectivity ASICs.
  • Strong scripting and automation skills (Python, Tcl).
  • Proven ability to lead complex PD execution in high-pressure tapeout environments.
  • Strong analytical and problem-solving skills with attention to detail.
  • Ability to synthesize ambiguous or conflicting requirements into execution plans.
  • Effective collaboration across global, cross-functional engineering teams.

Förmåner

  • Competitive annual discretionary bonus program.
  • Opportunity for annual RSU grants.
  • Highly competitive benefits package designed to support your success at work, at home, and at play.
#ASIC#Physical Design#Staff Engineer#SoC#Retimer#EDA#Cadence#Synopsys#Timing Closure#DFT#SerDes
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Företag

Qualcomm

Publicerade jobb

för 3 veckor sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Toronto, Canada

Kvalifikation

Masterexamen, Kandidatexamen, Doktorand

Sökande

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