Staff Applications Engineer, Synthesis and Formal Verification
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I korthet
Synopsys is seeking a Staff Applications Engineer in Sunnyvale, California, to provide technical expertise in synthesis and formal verification for ASIC design. You will manage customer relationships, debug complex issues, and guide methodology for Synopsys products, impacting silicon innovation.
Ansvarsområden
- Own technical relationships with customer RTL, synthesis, formal verification, and physical design teams.
- Debug complex synthesis and Formality issues, reproduce problems, isolate root causes, and deliver recommendations or escalate to R&D.
- Guide customers on RTL-to-netlist methodology using Fusion Compiler, Design Compiler, RTL Architect, and Formality.
- Analyze synthesis results, timing reports, constraint files, library characterization, and PPA outcomes.
- Create and maintain reusable scripts, reference flows, application notes, debug guides, and training materials.
- Translate recurring customer challenges and feature requests into clear use cases and product feedback for Synopsys R&D.
- Support technical evaluations, benchmarks, design reviews, and adoption of new synthesis and formal verification technologies.
Krav
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent hands-on experience in ASIC design or EDA applications.
- 5 or more years of hands-on experience in ASIC or SoC design, logic synthesis, formal equivalence checking, or EDA applications engineering, with at least one production design cycle or tapeout.
- Strong working knowledge of Verilog or SystemVerilog RTL, logic synthesis fundamentals, timing constraints (SDC), standard-cell libraries, and RTL-to-netlist design flows.
- Practical experience with formal equivalence checking tools, including the ability to set up comparisons, investigate setup issues, and analyze proof failures or inconclusive results.
- Proficiency with Tcl scripting and Linux command-line environments.
- Experience supporting customers and managing technical relationships.
Önskade kvalifikationer
- Direct experience with Synopsys Design Compiler, Fusion Compiler, RTL Architect, or Formality is a strong plus.
- Familiarity with static timing analysis tools like PrimeTime is a plus.
- Experience with UPF, low-power design, hierarchical SoCs, advanced process nodes, or physical-aware synthesis is valuable but not required.
- Ability to explain complex synthesis tradeoffs clearly and concisely.
- Skill in managing multiple customer engagements in parallel and communicating status and risks.
- Comfort working with incomplete information and asking effective questions.
- Attention to detail regarding synthesis decisions and their downstream impact.
Förmåner
- Comprehensive range of health, wellness, and financial benefits.
- Total rewards include both monetary and non-monetary offerings.
- Potential for annual bonus, equity, and other discretionary bonuses.
- Competitive total rewards package.
- Supportive and inclusive work environment.
Färdigheter
VerilogSystemVerilogTclLinuxSDCUPF
#ASIC#RTL#synthesis#formal verification#EDA#SoC#timing analysis#customer support#technical sales
Om Synopsys Inc
Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…
Företag
Synopsys IncPublicerade jobb
för 4 dagar sedan
Anställningstyp
Heltid
Arbetsform
På plats
Lön
129 000–193 000 US$ · Förhandlingsbar
Erfarenhetsnivå
Mellannivå
Platser
Sunnyvale, United States
Kvalifikation
Kandidatexamen, Ingen formell utbildning
Sökande
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