The Job

Sr Staff Mixed-Signal Verification Engineer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · QA och testning

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I korthet

Synopsys is seeking a Sr Staff Mixed-Signal Verification Engineer in Hyderabad to lead AMS verification strategy, test plans, and sign-off for complex IP projects. This role involves building and maintaining UVM/SystemVerilog environments, debugging complex analog-digital interface issues, and collaborating with cross-functional teams to ensure tapeout readiness.

Ansvarsområden

  • Own end-to-end AMS verification strategy, test plans, coverage models, and sign-off for mixed-signal blocks and subsystems across complex IP projects
  • Build and maintain UVM/SystemVerilog verification environments that integrate seamlessly with Verilog-A, Verilog-AMS behavioral models, and mixed-signal simulators
  • Debug complex analog-digital interface issues, simulation convergence problems, and cross-domain failures using waveform analysis and AMS-specific debug tools
  • Develop assertions, monitors, scoreboards, and automated verification infrastructure that catch real bugs
  • Drive AMS simulation efficiency improvements, optimize regression flows, and reduce debug turnaround time across the verification pipeline
  • Collaborate daily with analog designers, digital verification engineers, modeling teams, and architecture groups
  • Mentor verification engineers on AMS methodology, review test plans and environments, and drive best practices across the team

Krav

  • 8+ years of hands-on experience in AMS verification, with a proven track record of owning verification sign-off for mixed-signal designs
  • Expert-level proficiency in SystemVerilog and UVM, with deep understanding of testbench architecture, coverage-driven verification, and constrained-random methodologies
  • Strong working knowledge of Verilog-A and Verilog-AMS for behavioral modeling and mixed-signal simulation
  • Solid understanding of analog circuit behavior, including bias circuits, regulators, PLLs, ADCs, DACs, or other mixed-signal blocks
  • Experience with AMS simulators (Spectre AMS, Xcelium AMS, or similar) and waveform debug tools for mixed-signal analysis
  • Strong scripting skills in Python, Perl, or Tcl for automation, regression management, and infrastructure development

Önskade kvalifikationer

  • Experience with AI/ML-based verification techniques or automation frameworks is a strong plus

Förmåner

  • Comprehensive medical and healthcare plans
  • ETO and FTO Programs
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
  • Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
  • Retirement plans
  • Competitive salaries
#engineering#hardware#semiconductor#chip architecture#circuit design#verification#mixed-signal#analog#digital#IP#UVM#SystemVerilog#Verilog-A#Verilog-AMS#python#perl#tcl
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Företag

Synopsys Inc

Publicerade jobb

för 2 veckor sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Hyderabad, India

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