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Sr Staff Applications Engineer, HAV Solutions

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Synopsys is seeking a Sr Staff Applications Engineer for their HAV Solutions team in the United States. This role involves leading technical deployments of FPGA prototyping solutions for customers in AI/ML, automotive, hyperscaler, and aerospace sectors, driving the full ASIC-to-FPGA flow, and debugging complex interface IPs. The ideal candidate has 10+ years of experience in FPGA implementation, ASIC design, or related fields, with deep expertise in synthesis, timing closure, and verification tools.

Ansvarsområden

  • Lead technical deployments of HAPS-200 and ProtoCompiler for strategic customers building billion-gate SoCs across AI/ML, automotive, hyperscaler, and aerospace segments.
  • Drive the full ASIC-to-FPGA flow including partitioning, clock conversion, synthesis, place-and-route, timing closure, bitstream generation, and hardware bring-up on multi-FPGA systems.
  • Debug complex interface IP subsystems including DDR4/DDR5, LPDDR5/6/7, HBM, PCIe Gen3-6, CXL, UCIe, Ethernet, USB, AXI, and high-speed SerDes architectures.
  • Reproduce, analyze, and resolve critical customer escalations involving RTL issues, partitioning failures, timing violations, protocol mismatches, and hardware bring-up failures.
  • Collaborate directly with ProtoCompiler R&D and Product Management to validate new features, influence roadmap priorities, and represent customer requirements in product planning.
  • Develop and document reusable methodologies for partitioning strategies, clock architecture, debug instrumentation, verification environment adaptation, and hardware/software co-validation.
  • Mentor applications engineers globally, lead technical workshops and architecture reviews, and represent Synopsys at customer sites, conferences, and industry forums.

Krav

  • Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent hands-on experience.
  • 10+ years working in FPGA implementation, ASIC design, ASIC verification, hardware-assisted verification, FPGA prototyping, or emulation.
  • Deep expertise in FPGA synthesis, place-and-route, multi-FPGA partitioning, timing closure, and constraint development using Xilinx Vivado, Intel Quartus, or equivalent tools.
  • Strong working knowledge of SystemVerilog, UVM, assertions, functional coverage, and verification testbench architecture.
  • Hands-on experience with interface IP including PCIe, DDR4/DDR5, LPDDR, Ethernet, USB, AXI, CXL, or high-speed SerDes protocols.
  • Proficiency in Tcl, Python, or shell scripting for automation and flow development.

Önskade kvalifikationer

  • Direct experience with Synopsys HAPS and ProtoCompiler is a strong plus, as is experience with ZeBu, Palladium, Protium, or Veloce emulation platforms.
  • Ability to walk into a room with a customer's architecture team, understand their SoC in an hour, and identify key partitioning decisions.
  • Skilled in debugging PCIe link training or DDR interface calibration issues, and instrumenting designs to prove hypotheses.
  • Comfortable presenting technical tradeoffs to VPs and engineering directors.
  • Proactive in digging into logs, RTL, netlists, and hardware captures to understand issues.
  • Experience debugging designs using Verdi, runtime instrumentation, protocol analyzers, or assertion-based techniques.
  • Ability to explain the differences between emulation and prototyping with architectural tradeoffs.

Förmåner

  • Comprehensive range of health, wellness, and financial benefits.
  • Total rewards include both monetary and non-monetary offerings.
  • May be eligible for an annual bonus, equity, and other discretionary bonuses.
  • Competitive total rewards package.
#AI/ML#automotive#hyperscaler#aerospace#FPGA#ASIC#prototyping#verification#hardware-assisted verification#RTL design
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Företag

Synopsys Inc

Publicerade jobb

för 1 dag sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

United States

Kvalifikation

Kandidatexamen, Masterexamen, Doktorand

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