The Job

SOC Verification - Sr. Engineer

Technology, Data & Digital · Software & Web Development · QA & Testing

Gå med för uppdateringar

I korthet

Synopsys is seeking an experienced SOC Verification Sr. Engineer in Noida, India. This role involves building verification test plans, developing SystemVerilog testbenches with UVM, debugging complex issues, and mentoring junior engineers. The ideal candidate has a strong background in SOC verification methodologies and aims to ensure the quality and reliability of semiconductor products.

Ansvarsområden

  • Build verification test plans from design specs for processor-based SOCs, defining scope, coverage goals, and test scenarios.
  • Develop and maintain SystemVerilog testbenches and UVM environments, integrating Synopsys VIP and third-party verification IP.
  • Write and analyze SystemVerilog assertions and track code, toggle, and functional coverage to close verification gaps.
  • Debug complex simulation failures across multi-clock-domain SOC designs using VCS, waveform viewers, and scripting.
  • Mentor junior verification engineers through design bring-up, testbench architecture decisions, and debugging sessions.
  • Collaborate with architects, RTL designers, and post-silicon teams to align verification strategy with design intent.
  • Script automation flows using shell, Makefile, and Perl to improve regression efficiency and testbench reusability.

Krav

  • Bachelor's or Master's in Electronics Engineering or related field.
  • 2 to 5 years of hands-on experience in IP or SOC verification.
  • Strong working knowledge of SystemVerilog, UVM, and processor-based SOC verification environments.
  • Experience with VCS, waveform debugging tools, and integrating third-party VIPs into testbenches.
  • Solid understanding of AXI and AMBA protocol variants.
  • Proficiency in scripting with shell, Makefile, or Perl.
  • Working knowledge of ASIC design flow, RTL design concepts.

Önskade kvalifikationer

  • Experience with ARM core verification, USB, PCIe, or MIPI protocols is a strong plus.
  • Ability to take a design spec, identify potential issues, and build a verification plan.
  • Proven ability to root-cause issues in simulation failures.
  • Skill in explaining technical tradeoffs clearly to different stakeholders.
  • Ability to write readable, reusable, and extendable testbenches and assertions.
  • Experience leading debug sessions and mentoring junior engineers.
  • Keeps current on verification tools and methodologies.

Förmåner

  • Comprehensive medical and healthcare plans.
  • ETO and FTO Programs.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
  • ESPP: Purchase Synopsys common stock at a 15% discount.
  • Retirement Plans.
  • Competitive salaries.
#SOC#Verification#Engineering#Semiconductor#Noida
Synopsys Inc Logo

Företag

Synopsys Inc

Publicerade jobb

för 3 veckor sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Noida, India

Kvalifikation

Kandidatexamen, Masterexamen

Sökande

Ansök tidigt