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SOC Engineering, Sr Staff Engineer (STA)

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Synopsys is seeking a Sr Staff Engineer (STA) for SOC Engineering in Hyderabad, India. This role involves owning block-level STA signoff and contributing to full-chip timing closure for advanced process nodes, requiring 8+ years of experience and proficiency in STA tools and scripting.

Ansvarsområden

  • Own and execute block-level STA signoff and contribute to full-chip timing closure for advanced process nodes.
  • Perform STA debugging and closure (setup/hold, recovery/removal, clock gating, CDC-related timing assumptions as applicable) and drive issue resolution with design/PD teams.
  • Develop, validate, and maintain timing constraints (SDC) including clocks, generated clocks, exceptions, IO constraints, and mode/corner coverage.
  • Run and analyze power signoff/support flows (PrimePower / PT-PX) and correlate timing/power impacts of ECOs.
  • Support timing and power ECO generation, and validate fixes through signoff checks and regressions.
  • Work with synthesis/implementation teams to ensure tool correlation and correct interpretation of constraints and physical effects (parasitics, SI awareness, AOCV/POCV, derates).
  • Use Synopsys tools such as PrimeTime, PrimePower/PT-PX, PrimeClosure/Tweaker (as applicable) to meet PPA targets.
  • Build/maintain automation in TCL/Python/Perl to improve STA productivity, reporting, and regression quality.
  • Contribute to improving STA methodologies, checklists, and best practices; mentor junior engineers informally as needed.

Krav

  • Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics/Electrical Engineering or related field.
  • 8+ years of relevant experience in STA / timing closure (block ownership expected; full-chip exposure preferred).
  • Strong hands-on experience in Constraints development/validation (SDC).
  • STA signoff across modes/corners, including MMMC concepts.
  • Timing closure debugging and ECO validation.
  • Power analysis/support (PrimePower / PT-PX exposure preferred).
  • Proficiency with Synopsys tools such as PrimeTime (required).
  • Strong scripting skills in TCL (required).

Önskade kvalifikationer

  • Exposure to advanced nodes (e.g., 16/12/10/7nm; exposure to 5nm is a plus).
  • Comfortable owning key timing deliverables for blocks and contributing to full-chip closure in collaboration with physical design, synthesis, and verification teams.
  • Solid experience across the timing closure lifecycle—constraints development and validation, STA signoff, power analysis, and ECO support.
  • Proficiency with PrimePower/PT-PX, PrimeClosure/Tweaker (preferred).
  • Working knowledge/exposure to Fusion Compiler/ICC2 or DC, parasitic extraction concepts (e.g., StarRC), and signoff correlation (preferred).
  • Proficiency in Python/Perl (preferred).
  • Understanding of low-power and high-frequency design considerations (UPF awareness is a plus).

Förmåner

  • Competitive salaries.
  • Comprehensive medical and healthcare plans.
  • ETO and FTO Programs for time away.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
  • ESPP with a 15% discount and a 24-month look-back.
  • Retirement plans.
  • Comprehensive range of health, wellness, and financial benefits.
#SOC#STA#Timing Closure#Signoff#Semiconductor
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Företag

Synopsys Inc

Publicerade jobb

för 1 månad sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Hyderabad, India

Kvalifikation

Kandidatexamen, Masterexamen

Sökande

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