SOC Engineering, Sr Staff Engineer- RTL Design
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Synopsys is looking for a Sr Staff Engineer for RTL Design with extensive experience in RTL design, signoff, and verification using tools like Spyglass and Design Compiler. The role involves developing timing constraints, performing synthesis and formal verification, and integrating IP blocks for cutting-edge semiconductor solutions.
Ansvarsområden
- Run RTL quality signoff using Spyglass for LINT, CDC, and RDC checks across IP blocks, subsystems, and full SoC designs.
- Develop timing constraints in SDC for synthesis and static timing analysis.
- Execute preliminary synthesis runs using Design Compiler or Fusion Compiler to validate RTL synthesizability, area, and timing feasibility.
- Perform formal equivalence checking with Formality to verify RTL-to-gate consistency.
- Integrate third-party and Synopsys IP into customer SoCs and subsystems.
- Create and modify RTL design blocks to meet customer-specific requirements.
- Collaborate with verification, implementation, and architecture teams to close signoff issues.
Krav
- Bachelor's or Master's in Electronics Engineering, Electrical Engineering, or Computer Engineering.
- 8+ years of hands-on experience in RTL design and verification.
- Proven experience performing static verification using Spyglass or equivalent tools for LINT, CDC, and RDC analysis.
- Strong working knowledge of synthesis tools such as Design Compiler or Fusion Compiler.
- Hands-on experience with Formality or equivalent formal verification tools.
- Solid conceptual understanding of clock domain crossing, reset domain crossing, and common design pitfalls.
- Experience integrating IP blocks into subsystems or SoCs.
- Familiarity with scripting in Tcl, Python, or Perl is a strong plus.
Önskade kvalifikationer
- Ability to analyze CDC reports and identify critical violations.
- Skill in writing usable timing constraints for implementation teams.
- Ability to push back on architectural decisions that may cause signoff issues.
- Comfortable working directly with customers.
- Staying current on best practices for RTL design as nodes shrink and complexity grows.
- Ability to context-switch between different levels of design complexity.
Förmåner
- Competitive salaries
- Comprehensive medical and healthcare plans.
- ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
- ESPP: Purchase Synopsys common stock at a 15% discount.
- Retirement Plans.
- Opportunities to work on cutting-edge semiconductor designs powering AI, automotive, 5G, and IoT applications.
#SOC#RTL Design
Företag
Synopsys Inc
Publicerade jobb
för 6 dagar sedan
Anställningstyp
Heltid
Arbetsform
På plats
Erfarenhetsnivå
Senior
Platser
Noida, India
Kvalifikation
Kandidatexamen, Masterexamen
Sökande
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