The Job

SoC Verification Senior Engineer

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I korthet

Synopsys is looking for a Senior SoC Verification Engineer in Ho Chi Minh City, Vietnam, to design and develop cutting-edge semiconductor solutions. This role requires expertise in System Verilog and UVM, with a focus on finding critical bugs before tapeout and ensuring product reliability.

Ansvarsområden

  • Define block and subsystem verification plans that map directly to design specifications and protocol requirements
  • Build UVM testbenches in System Verilog, including agents, scoreboards, coverage models, and assertion monitors
  • Write constrained random and directed tests that exercise protocol compliance, corner cases, and error injection scenarios
  • Debug RTL and testbench failures using simulators and waveform analysis to root cause and resolve issues
  • Collaborate with RTL designers and global verification engineers to align on design intent and coverage goals
  • Apply formal verification techniques to prove properties and close coverage gaps
  • Drive verification closure by tracking coverage metrics and iterating on test plans until signoff

Krav

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science
  • 2+ years of hands-on design verification experience in the semiconductor industry
  • Strong proficiency in System Verilog and UVM for building testbenches and implementing coverage
  • Working knowledge of at least one protocol such as AMBA, PCI Express, CXL, UCIe, Ethernet, HBM, or DDR
  • Experience with industry standard simulators like VCS, Xcelium, or Questa, and version control systems
  • Solid scripting skills in Python, Perl, or Tcl for automation and regression management

Önskade kvalifikationer

  • You can take a protocol spec and translate it into a verification plan that covers what matters, not just what is easy to test
  • When a regression fails before a milestone, you dig into the waveform and find the root cause instead of waiting for triage
  • You communicate clearly with RTL designers about what you found and what needs to change, without blame
  • You manage multiple verification tasks in parallel without losing track of coverage goals or debug priorities
  • You ask questions when something in the design does not make sense, and you do not assume someone else will catch it

Förmåner

  • Comprehensive medical and healthcare plans
  • ETO and FTO Programs
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
  • ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
  • Retirement Plans
  • Competitive salaries
#SoC Verification#Senior Engineer#Semiconductor#Hardware Engineering#Chip Architecture#Circuit Design#Verification#System Verilog#UVM#RTL Design#AI Accelerators#Autonomous Vehicles#Protocols#Python#Perl#Tcl#VCS#Xcelium#Questa
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Företag

Synopsys Inc

Publicerade jobb

för 4 veckor sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Ho Chi Minh City, Vietnam

Kvalifikation

Kandidatexamen, Masterexamen

Sökande

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