SoC RTL Design - Sr Staff

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I korthet

Synopsys is looking for a Sr Staff SoC RTL Design Engineer in Noida, India, responsible for designing and signing off RTL that ships in silicon. The role involves using tools like Spyglass for quality checks, developing timing constraints, and performing synthesis and formal verification to ensure design quality and reduce respin risks for customers.

Ansvarsområden

Run RTL quality signoff using Spyglass for LINT, CDC, and RDC checks across IP blocks, subsystems, and full SoC designs
Develop timing constraints in SDC for synthesis and static timing analysis, ensuring constraints accurately reflect design intent and architecture
Execute preliminary synthesis runs using Design Compiler or Fusion Compiler to validate RTL synthesizability, area, and timing feasibility before handoff
Perform formal equivalence checking with Formality to verify RTL-to-gate consistency across design revisions and ECOs
Integrate third-party and Synopsys IP into customer SoCs and subsystems, resolving integration issues related to clocking, reset, and interface protocols
Create and modify RTL design blocks to meet customer-specific requirements, working within established design guidelines and delivery timelines
Collaborate with verification, implementation, and architecture teams to close signoff issues and ensure RTL quality gates are met before tapeout

Krav

Bachelor's or Master's in Electronics Engineering, Electrical Engineering, or Computer Engineering with 8+ years of hands-on experience in RTL design and verification
Proven experience performing static verification using Spyglass or equivalent tools for LINT, CDC, and RDC analysis on complex digital designs
Strong working knowledge of synthesis tools such as Design Compiler or Fusion Compiler, including constraint development and synthesis quality checks
Hands-on experience with Formality or equivalent formal verification tools for RTL-to-gate equivalence checking
Solid conceptual understanding of clock domain crossing, reset domain crossing, and common design pitfalls that lead to metastability or functional failures
Experience integrating IP blocks into subsystems or SoCs, including resolving interface, clocking, and protocol issues

Önskade kvalifikationer

Familiarity with scripting in Tcl, Python, or Perl to automate checks, reporting, and design flows is a strong plus

Förmåner

Comprehensive medical and healthcare plans
ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Retirement plans
Competitive salaries

#RTL Design#SoC#Synopsys#Hardware Engineering#Semiconductor#Chip Architecture#Circuit Design#Verification#Spyglass#CDC#RDC#SDC#Synthesis#Formal Verification#IP Integration#AI#Automotive#5G#IoT

Företag

Synopsys Inc

Publicerade jobb

för 17 timmar sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Noida, India

Kvalifikation

Kandidatexamen, Masterexamen

Sökande

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