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SMMU Senior Lead Design Verification Engineer

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Qualcomm is seeking a Senior Lead Design Verification Engineer for their Bangalore, India office. This role involves full ownership of the System Memory Management (SMMU) IP test bench and associated collaterals for next-generation SoCs, requiring expertise in UVM and System Verilog.

Ansvarsområden

  • Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage)
  • Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench
  • Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure
  • Debug of regression signatures and identifying bug fixes
  • Developing/Deploying scripts/tools for validation (Certitude, VC Formal, Fishtail)
  • Debug and root cause post silicon issues in collaboration with Design, SW and test teams
  • Work with SoC level performance modeling team on latency, bandwidth analysis

Krav

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree and 2+ years of experience. OR PhD and 1+ year of experience.
  • Strong debugging, Analytical and problem-solving skills
  • Expertise on UVM, System Verilog coding
  • Knowledgeable about ARM bus protocols (AXI, AHB, APB, CHI), Virtual Memory concepts, SoC system architecture
  • Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved

Önskade kvalifikationer

  • Post-si bring-up and HW-SW debug experience would be a plus.
  • Knowledge & exposure to silicon debug tool chains would be an added advantage
  • Communication and collaboration skills to work with a large world-wide design organization

Förmåner

  • Ownership of System Memory Management [SMMU] IP test bench and collaterals for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories.
  • Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage)
  • Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench
  • Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure
  • Debug of regression signatures and identifying bug fixes
  • Developing/Deploying scripts/tools for validation (Certitude, VC Formal, Fishtail)
  • Debug and root cause post silicon issues in collaboration with Design, SW and test teams
  • Work with SoC level performance modeling team on latency, bandwidth analysis
#System Memory Management#SMMU#IP test bench#System-on-chip#SoC#smartphones#tablets#ARM SMMU architecture#DDR memory#virtual to physical address translation#dynamic allocation#access control#UVM#System Verilog#AXI#AHB#APB#CHI#ARM bus protocols#Virtual Memory#SoC system architecture#Monitors#Scoreboards#Sequencers#post silicon#HW-SW debug
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Företag

Qualcomm

Publicerade jobb

för 1 månad sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Bangalore, India

Kvalifikation

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