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Serdes PHY Analog Design Engineer

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Qualcomm is seeking an experienced analog circuit designer with 8+ years of experience to work on high-speed SerDes PHYs for next-generation SoCs. The role involves designing low-power analog circuits, including building blocks and PLLs, and requires hands-on experience from schematic design to post-silicon bring-up. Collaboration with cross-functional teams is essential for this position.

Ansvarsområden

  • Directly involved in delivering next-generation custom PHY designs for SoCs.
  • Part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond.
  • Design goals include low-power analog designs to address Qualcomm's low-power wireless products.
  • Hands-on experience in Analog circuit design, including designing multiple analog building blocks (LDO, high speed TX and RX, Bias, Reference).
  • Experience with Analog and/or Digital PLLs for frequency synthesis and/or SerDes applications (Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers).
  • Experience with PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ).
  • Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up.
  • Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY.

Krav

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
  • Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
  • PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
  • Experienced (8+ years) analog circuit designers.
  • Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc.
  • Experience with Analog and or Digital PLLs for frequency synthesis and/or SerDes applications
  • Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up.
  • Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY.
  • For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc.
  • Understanding of advance Finfet process effects on designs and layout is required.
  • Experience in using SPICE simulators, adexl & virtuoso.
  • Experience with post-Si bring-up and debug is must.
  • Master/Bachelor in Electronics
  • Shell/Perl-python scripting to automate circuit design and verification work.
  • Able to work with teams across the globe and possess good communication and presentation skills.

Önskade kvalifikationer

  • Mixed signal design experience
  • Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage.

Förmåner

  • Qualcomm is an equal opportunity employer.
  • Qualcomm is committed to providing an accessible process for individuals with disabilities.
  • Qualcomm is committed to making our workplace accessible for individuals with disabilities.
#Serdes PHY#Analog Design#Hardware Engineering
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Företag

Qualcomm

Publicerade jobb

för 1 dag sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Bangalore, India

Kvalifikation

Kandidatexamen, Masterexamen, Doktorand

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