The Job

SerDes Analog Design Engineer, Sr Staff

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

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Synopsys is seeking a highly motivated Sr Staff SerDes Analog Design Engineer in Seongnam-si, South Korea. This role involves designing and developing cutting-edge semiconductor solutions, focusing on analog and mixed-signal building blocks for SerDes designs. The ideal candidate will have extensive experience in CMOS fundamentals, circuit optimization, and working collaboratively with digital teams.

Ansvarsområden

  • Ensuring analog sub-block performance adheres to SerDes standards and architecture document specifications.
  • Identifying and refining circuit implementations to achieve optimal power, area, and performance targets.
  • Proposing design and verification strategies that efficiently use simulator features to ensure the highest quality design.
  • Overseeing physical layout to minimize the effect of parasitics, device stress, and process variation.
  • Partnering with digital RTL engineers on the verification of calibration, adaptation, and control algorithms for analog circuits.
  • Presenting simulation data for peer and customer review.
  • Taking ownership of analog and mixed-signal building blocks that are integrated as part of a larger SerDes design.
  • Documenting design features and test plans.
  • Consulting on the electrical characterization of your circuit within the SerDes IP product.

Krav

  • Ph.D. with 5+ years, or MSc with 10+ years of SerDes/High-Speed analog design experience.
  • Familiarity with the transistor-level circuit design of fundamental analog and mixed-signal building blocks.
  • Silicon-proven experience implementing circuits for analog and mixed-signal building blocks.
  • Design experience with some of the following SerDes sub-circuits: receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC.
  • Experience optimizing CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
  • Awareness of ESD issues (i.e. circuit techniques, layout) and design for reliability (i.e. electro-migration, IR, aging, etc.).
  • Experience with EDA tools for schematic entry, physical layout, and design verification.
  • Knowledge of SPICE simulators and simulation methods.
  • Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
  • Experience with TCL, Perl, C, Python, MATLAB.

Önskade kvalifikationer

  • Collaborative and open-minded, thriving in a team-oriented environment.
  • Detail-oriented with strong analytical and problem-solving skills.
  • Proactive and self-motivated with a strong sense of ownership and accountability.
  • Excellent communication skills, capable of presenting complex technical information clearly.
  • Flexible and adaptable, able to manage multiple priorities and deadlines.
  • Passionate about continuous learning and staying updated with industry trends.

Förmåner

  • Comprehensive medical and healthcare plans that work for you and your family.
  • In addition to company holidays, we have ETO and FTO Programs.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
  • Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
  • Save for your future with our retirement plans that vary by region and country.
  • Competitive salaries.
#SerDes#Analog Design#Engineering#Semiconductor#IP Integration
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Företag

Synopsys Inc

Publicerade jobb

för 1 vecka sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Seongnam-si, South Korea

Kvalifikation

Doktorand, Masterexamen

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