Senior Staff Verification Engineer, High-Speed Interconnect

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · QA och testning

I korthet

Synopsys is looking for a Senior Staff Verification Engineer to own end-to-end verification of high-speed interconnect IP like UCIe, PCIe, or DDR. This role involves building UVM testbenches, debugging complex failures, and mentoring junior engineers. The ideal candidate has 7+ years of experience in ASIC/SoC verification and deep knowledge of high-speed protocols.

Ansvarsområden

Own end-to-end verification of UCIe, PCIe, or DDR IP blocks, from test planning and environment bring-up through coverage closure and sign-off
Build and extend UVM testbenches in SystemVerilog, including agents, sequencers, scoreboards, coverage models, and protocol checkers
Write directed and constrained-random tests that stress protocol compliance, corner cases, and multi-layer interactions
Debug complex RTL and testbench failures using Synopsys Verdi, including waveform analysis, protocol trace, and transaction-level debug
Translate protocol specifications into executable test plans, assertions (SVA), and functional coverage models that map to real silicon risk
Collaborate with design, architecture, and silicon validation teams on bug triage, ECO impact analysis, and bring-up readiness
Mentor verification engineers on UVM methodology, debug techniques, and protocol understanding, and contribute to design and verification reviews

Krav

7+ years of hands-on ASIC or SoC design verification experience, with at least 3 years on protocol-heavy IP
Deep working knowledge of at least one high-speed protocol: PCIe, UCIe, or DDR, with the ability to read specs and build compliant testbenches
Strong UVM methodology experience, including building agents, writing constrained-random sequences, implementing scoreboards, and closing functional coverage
Solid SystemVerilog skills, including object-oriented programming, constrained-random stimulus generation, and SystemVerilog Assertions (SVA)
Proven ability to debug complex failures using Synopsys Verdi or equivalent tools (FSDB, protocol analyzers, transaction-level debug)
Experience with industry simulators such as VCS, Xcelium, or Questa, and familiarity with regression and coverage tools like URG
B.Tech or M.Tech in Electronics, VLSI, Electrical Engineering, or related discipline

Önskade kvalifikationer

Working knowledge of a second protocol (PCIe, UCIe, DDR, CXL) is a strong plus

Förmåner

Comprehensive medical and healthcare plans
ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Retirement plans
Competitive salaries

#hardware engineering#verification#high-speed interconnect#semiconductor#ASIC#SoC#IP verification#UVM#SystemVerilog#PCIe#UCIe#DDR#AI#compute systems

Företag

Synopsys Inc

Publicerade jobb

för 1 vecka sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Hyderabad, India

Kvalifikation

Kandidatexamen, Masterexamen

Sökande

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