The Job

Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet)

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I korthet

Synopsys is looking for a Senior Staff Interface IP Verification Engineer to own the end-to-end verification of critical Interface IP blocks like PCIe, CXL, DDR, and Ethernet. The role involves building UVM environments, defining verification strategies, and leading technical discussions to ensure silicon quality and reliability for AI platforms and cloud infrastructure.

Ansvarsområden

  • Own end-to-end verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet, from architecture review through silicon signoff
  • Build and evolve UVM-based verification environments that are reusable across product lines and scalable for future protocol generations
  • Define verification strategies and test plans that account for protocol compliance, performance corner cases, and system-level integration scenarios
  • Develop constrained-random, coverage-driven test scenarios using SystemVerilog and UVM, targeting functional coverage closure and signoff quality
  • Debug complex multi-layer issues spanning RTL logic, protocol state machines, timing, and testbench infrastructure using VCS or equivalent simulators
  • Collaborate with architecture, design, firmware, and systems teams to identify and resolve issues early in the development cycle
  • Mentor verification engineers on UVM methodology, coverage analysis, debugging techniques, and verification best practices

Krav

  • Bachelor's or Master's in Electrical Engineering or Computer Engineering with 8+ years of hands-on ASIC or SoC verification experience
  • Deep expertise in SystemVerilog and UVM methodology, with a track record of building scalable verification environments from the ground up
  • Strong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet, with the ability to read specs and translate them into verification requirements
  • Proven experience developing constrained-random and coverage-driven verification solutions that achieve functional signoff
  • Solid debugging skills across RTL, verification infrastructure, and protocol compliance, with experience using industry-standard simulators like VCS or ModelSim

Önskade kvalifikationer

  • Experience with verification IP development, assertion-based verification, or formal methods is a strong plus
  • Knowledge of modern SoC architectures and high-speed communication interfaces is a plus

Förmåner

  • Comprehensive medical and healthcare plans that work for you and your family.
  • In addition to company holidays, we have ETO and FTO Programs.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
  • Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
  • Save for your future with our retirement plans that vary by region and country.
  • Competitive salaries.
#hardware#verification#semiconductor#interface IP#PCIe#CXL#DDR#Ethernet#ASIC#SoC
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Företag

Synopsys Inc

Publicerade jobb

för 1 vecka sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Bengaluru, India

Kvalifikation

Kandidatexamen, Masterexamen

Sökande

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