Senior Physical Design Engineer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

I korthet

Microsoft is seeking a Senior Physical Design Engineer to contribute to the design and development of state-of-the-art computer chips for Azure Cobalt. This role involves end-to-end execution of silicon designs, from synthesis through place-and-route, ensuring all signoff stages are completed.

Ansvarsområden

Drive end-to-end execution from synthesis through place-and-route for large designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
Responsible for clock construction and CTS.
Drive methodology exploration activities to optimize SOC blocks for clock construction and related methodology.
Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners.
Responsible for RTL to GDS implementation in Physical Design domain.
Influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach.
Foster collaboration across teams to deliver the possible solutions, aligned with a One Microsoft mindset.
Demonstrate technical expertise across various domains of Physical Design.
Clear communications on project status & planning.
Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.

Krav

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements.
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations.
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information.
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport.
Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Önskade kvalifikationer

BS/MS in Electrical or Computer Engineering or any related degree
Min 7+ years of experience in semiconductor design.
Communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
Proven track record in Physical Design domain implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.
Production silicon tape-outs experience in advanced foundry process nodes.
Experience in low power design methodology for SOC
Thorough understanding of SOC or subsystem design trade-offs across power, performance, and area (PPA).
Familiarity with various clock construction strategies for high speed designs
Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff, Formal Equivalence, and Low Power Verification.
Own complete PD execution of medium to large-size SOC block.
Be fully hands-on in technical domain ownerships as individual contributor and collaborate cross-team as required.
Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues.
Problem-solving and data analysis skills.
Ability to communicate effectively with cross-functional teams.

Förmåner

The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year.
There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Certain roles may be eligible for benefits and other compensation.
Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Färdigheter

RTLDFTPowerTimingSynthesisPlace and RouteFormal EquivalenceLow Power Design

#Hardware Engineering#Silicon Engineering#Physical Design

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Företag

Microsoft

Publicerade jobb

för 2 dagar sedan

Anställningstyp

Heltid

Arbetsform

Hybrid

Lön

119 800–234 700 US$ / år

Erfarenhetsnivå

Senior

Platser

United States

Kvalifikation

Doktorand, Masterexamen, Kandidatexamen, Ingen formell utbildning

Sökande

Ansök tidigt

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Ansvarsområden

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Förmåner

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