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Senior IP Micro Architect -Sr Lead/Staff

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

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I korthet

Qualcomm is seeking a Senior IP Micro Architect with extensive experience in defining and delivering complex custom IPs from concept to silicon. The role involves driving architecture and microarchitecture definition, RTL development, and performance optimization for Infrastructure IPs, NoC, PCIe, CXL, and memory systems. Requires strong technical leadership and hands-on design expertise with Verilog/SystemVerilog.

Ansvarsområden

  • Drive architecture and microarchitecture definition of complex custom Infrastructure IPs.
  • Develop detailed microarchitecture specifications including datapath design, control logic, packet formats, flow control, ordering rules, coherency mechanisms, and state machines.
  • Lead RTL development and collaborate closely with verification, physical design, firmware, and SoC integration teams.
  • Evaluate and optimize architecture trade-offs across performance, power, area, scalability, latency, and implementation complexity.
  • Design and develop high-performance interconnect, memory, and protocol-centric IP solutions.
  • Drive design reviews, microarchitecture reviews, and technical decision-making across multiple projects.
  • Support verification planning, debug, emulation, FPGA validation, and silicon bring-up activities.
  • Ensure RTL quality through lint, CDC/RDC, synthesis, and design signoff methodologies.
  • Mentor junior engineers and provide technical leadership within the IP development team.
  • Stay abreast of emerging technologies in AI infrastructure, scale-up fabrics, memory systems, and high-speed interconnects.

Krav

  • 8-15 years of experience in SoC/IP architecture, microarchitecture, and RTL design.
  • Proven experience defining and delivering complex custom IPs from concept through production silicon.
  • Strong experience in architecture and microarchitecture development of one or more of the following: Infrastructure IPs, NoC, interconnect fabrics, memory subsystem IPs, cache coherency solutions, or high-speed interface IPs.
  • Strong understanding of computer architecture, SoC architecture, digital design methodologies, performance modeling and analysis, synchronization and flow control mechanisms, and high-performance data movement architectures.
  • Hands-on RTL design experience using Verilog/SystemVerilog.
  • Experience with design signoff methodologies including lint, CDC/RDC, synthesis, and timing closure fundamentals.
  • Strong debugging, analytical, and problem-solving skills.
  • Excellent verbal and written communication skills.
  • Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.

Önskade kvalifikationer

  • Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
  • Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
  • PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
#IP#Microarchitecture#Custom Protocol Design#RTL Implementation#Performance Optimization#Silicon Delivery#Infrastructure IP#NoC#PCIe#CXL#Memory Systems#Cache Coherency#UALink#ESUN#Interconnect Fabrics#SoC#Custom IP Team#SoC Integration#Verilog#SystemVerilog#Lint#CDC#RDC#Synthesis#Timing Closure
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Företag

Qualcomm

Publicerade jobb

för 2 dagar sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Bangalore, India

Kvalifikation

Kandidatexamen, Masterexamen, Doktorand

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