Senior Group Technical Architect

Job Summary

Experience 15 to 20 years Define ASIC/SoC verification strategy
Full chip testplan development
Full chip TB Architecture definition
UVM based testbench development
C based TB development
SV functional coverage, Assertions coding
Test case development, coding, execution, bug analysis
Gate Level Simulation
Regressions, coverage analysis
Own and execute verification closure
Own and lead End-End projects
Engineering Execution
Management & Strategy

Key Responsibilities

Has participated in multiple ASIC/SoC verification till  tape out stage
Experience writing ASIC/SoC test plans
Experience in ASIC/SoC Testbench definition. Experience to Build and maintain reusable block-level and sub-system testbenches using System Verilog and the Universal Verification Methodology (UVM)."
Experience in developing TB components for SOC with C, SV
Expertise & hands-on experience in OVM/UVM methodologies using SV
Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans."
Experience in developing TB components, including functional coverage implementation and assertion coding
Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.
Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.
Experience in SOC C based tests coding & debugging"
Experience in Gate level simulation & netlist debugging
Experience in regression failure analysis
Functional and Code Coverage closure"
Experience in Utilizing scripting languages like Perl/Shell scripting to automate regression tests and parse large simulation log files.

Skill Requirements

Processor Knowledge: Strong understanding of CPU/GPU architectures, cache coherency, and memory controllers (e.g., DDR4/DDR5, HBM) is highly desirable.
Tools: Expert proficiency with industry-leading EDA simulators, debuggers (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verd), and emulation platforms. 
"Protocols: 
Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C,PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE)."

Other Requirements

Scripting: Advanced capability in Python, Tcl, or Perl to create custom automation infrastructure for regressions and metrics tracking.
Strategic Thinking: Ability to foresee technical risks weeks or months in advance and proactively implement mitigation strategies.
Influence: Strong leadership and communication skills to guide cross-functional teams and align stakeholders on technical directions.