Senior DFX Engineer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · Inbyggda system

I korthet

Ericsson seeks a Senior DFX Engineer in Austin, Texas, to join their ASICs team. This on-site role involves designing, implementing, and verifying DFX (Design for Testability) and SLM (Silicon Lifecycle Management) capabilities for complex ASICs, utilizing AI and collaborating with global teams.

Ansvarsområden

Strengthen the DFX & SLM group as the technical authority for silicon lifecycle management.
Strategize, architect, plan, design/implement & verify DFT and SLM capabilities across multiple ASIC programs.
Extend silicon lifecycle capability in the field, including in-system test, telemetry, monitoring, diagnostics, and repair.
Partner with the Test Team to define overall Test Strategy.
Partner with Physical Design teams to develop complex SOCs.
Work with EDA Vendors, ASIC partners & CAD team to define next-generation DFT/SLM flows and methodology.
Apply AI as a tool in daily execution for automating flows, accelerating debug and triage, and extracting insights from telemetry.
Mentor and coach junior engineers within the team.
Collaborate with cross-site/geography teams for efficient deliverables.

Krav

Several years of hands-on, in-industry experience in SOC/IP/ASIC design with an emphasis on DFX (DFT/DFD/DFM).
Experience in DFX Verification (Memory BIST, JTAG, Boundary Scan, In-field Tests, Custom IP Test Interface).
Minimum Education: BSEE.
Working knowledge of DFX standards and practices, ATPG, Scan, JTAG, iJTAG, BIST, including trade-offs.
Experience with SOC level DFT planning, architecture, and execution.
Exposure to Silicon Lifecycle Management: in-field/in-system test, telemetry-driven monitoring and diagnostics, and RAS concepts.
Good focus on automation & infrastructure to enable efficient execution pipeline within DFX function.
Experience applying AI/ML to engineering workflows (debug, triage, data analysis, flow automation) or a demonstrated drive to build it into daily execution.
Experience with post-silicon debug, yield bring-up, test-time and pattern delivery.
Continuous drive to improve flows, methodology and architecture for scalability.
Understanding of Physical design implementation flows and methods for smooth DFT integration.

Önskade kvalifikationer

Familiarity with IEEE 1149.1, 1687, and 1838 is a plus.
Experience with efficient and quality handoffs for DFT integration in physical design.

Förmåner

Competitive salary range with annual bonus potential.
Excellent health benefits including medical and dental plan options.
Company credits towards medical and dental premiums.
401(k) Plan with automatic 3% company contribution and dollar-for-dollar match on the first 3% of eligible pay, plus 50 cents on the next 2%.
Company-paid basic life insurance and accidental death and dismemberment coverage.
Company-paid short-term and long-term disability coverage.
Optional participation in Ericsson’s Stock Purchase Plan.
Minimum of 15 days of accrued vacation.
Up to 3 personal days per year.
11 annual holidays.
8 hours of volunteer time.
80 hours of sick time annually.
Up to 16 weeks of paid maternity leave.
6 weeks of parental or adoption leave at 100% of pay.
Financial wellness programs.
Educational assistance.
Matching gifts.
Recognition programs.

Färdigheter

DFTDFDDFMMemory BISTJTAGBoundary ScanIn-field TestsCustom IP Test InterfaceATPGScaniJTAGBISTIEEE 1149.1IEEE 1687IEEE 1838AIML

#ASIC#DFX#DFT#SLM#EDA#AI

Om Ericsson

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