Senior Designer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

I korthet

Wir suchen hochmotivierte Memory Design Engineers mit 3-5 Jahren Erfahrung im Design, der Entwicklung und der Optimierung von Speicher-IPs (SRAM, ROM, Register Files etc.) für fortschrittliche Halbleiterknoten. Die Rolle umfasst Schaltungsdesign, Charakterisierung und die Zusammenarbeit mit RTL-, Layout- und Verifikationsteams.

Ansvarsområden

Design and develop high-performance, low-power memory circuits (SRAM/ROM/Register Files).
Work on bitcell design, peripheral circuits, sense amplifiers, decoders, and control logic.
Drive memory architecture definition based on SoC requirements.
Optimize designs for power, performance, and area (PPA).
Perform transistor-level design and simulations (SPICE, Spectre, HSPICE).
Conduct corner analysis, Monte Carlo simulations, and variation-aware design.
Debug design issues across PVT conditions.
Interface with RTL, Physical Design, DFT, and Product teams for seamless integration.
Support layout teams for custom layout guidance and ensure DRC/LVS compliance.
Participate in design reviews, tapeouts, and silicon validation.
Analyze post-silicon results and debug failures.
Work on yield improvement and reliability issues (aging, EM, IR drop).
Develop scripts (Python, Perl, Shell) to automate design and verification tasks.

Krav

3-5 years of experience
Strong understanding of CMOS fundamentals
Strong understanding of Memory architectures (SRAM, ROM, emerging memory is a plus)
Strong understanding of Low-power design techniques
Expertise in Cadence Virtuoso, Spectre/HSPICE
Expertise in Layout tools & verification flows (DRC/LVS)
Knowledge of STA basics, timing closure for memory interfaces
Knowledge of Yield, variability, and reliability analysis
Strong problem-solving and debugging skills
Ability to work across cross-functional teams
Good communication and documentation skills

Önskade kvalifikationer

Experience with memory compilers or embedded memory IP development
Knowledge of FinFET technologies
Experience in high-speed interfaces or cache design

Förmåner

You'll supercharge your potential.
You'll find your career.
And you'll find your spark.
All at a place that knows that helping its customers stay on top starts by putting its people first.

Färdigheter

SRAMROMRegister FilesLow-power designCMOSCadence VirtuosoSpectreHSPICEDRCLVSSTAPythonPerlShell scripting

#memory IP#SRAM#ROM#Register files#semiconductor#circuit design#characterization#RTL#layout#verification#SoC#PPA#transistor-level design#simulations#SPICE#Spectre#HSPICE#corner analysis#Monte Carlo simulations#variation-aware design#PVT#Physical Design#DFT#Product#DRC/LVS#tapeouts#silicon validation#post-silicon results#yield improvement#reliability issues#aging#EM#IR drop#automation#Python#Perl#Shell#CMOS#low-power design#Cadence Virtuoso#STA#timing closure#memory compilers#embedded memory IP#FinFET#high-speed interfaces#cache design

Om HCLTech

Supercharging progress through technology and innovation

HCLTech is a global technology company, home to 219,000+ people across 54 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending September 2022 totaled $12.1 billion. To learn how we can supercharge progress for…

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