Senior Designer

Technology, Data & Digital · Software & Web Development · Backend · QA & Testing

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HCLTech is seeking a Senior Designer with a strong understanding of ASIC/SoC life cycles and experience in testplan and verification strategy documentation. The role involves building and maintaining reusable testbenches using SystemVerilog and UVM, developing test components with C/SV, and debugging complex simulation failures. A Bachelor's or Master's degree in a related engineering field is required.

Job Summary

Good understanding of ASIC/SoC life cycle

Experience writing ASIC/SoC testplans

Experience in writing verification strategy document

1.Experience in ASIC/SoC Testbench definition
2.Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and the Universal Verification Methodology (UVM).

1. Experience in developing TB components for SOC with C, SV

1.Expertise & hands-on experience in OVM/UVM methodologies using SV
2.Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.

1. Experience in developing TB components, including functional coverage implementation and assertion coding
2. Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.
3.Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.
4. Experince in SOC C based tests coding & debugging

Experience in Gate level simulation & netlist debugging

Exeprince in regression failure analayiss
Functioncal and Code Coverage closure

Bachelor's or Master's degree in Electronics & Communication Engineering (ECE),
Electrical Engineering (EE), VLSI Design, or a closely related field

 

 

Languages: Proficiency in Verilog, SystemVerilog, and core concepts of UVM.

Digital Logic: Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts. 

EDA Tools: Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verdi). 

Protocols: Basic understanding of standard bus protocols like AMBA (AXI, AHB, APB) or peripheral protocols (SPI, I2C, PCIe). 

Scripting: Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation.

Key Responsibilities

1. To work closely with stakeholders to understand and refine design requirements.
2. To develop prototypes and proof-of-concept implementations to validate design decisions.
3. To mentor junior designers ,share knowledge and expertise through training sessions and documentation.
4. To collaborate with cross functional teams and other stakeholders to align software design with overall project goals.
5. To work with quality assurance teams to establish and maintain high-quality.

Skill Requirements

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Other Requirements

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#senior-designer#asic#soc#verification#systemverilog#uvm#testbench development#digital logic#eda-tools#bangalore
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Företag

HCLTech

Publicerade jobb

för 1 vecka sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Bangalore, India

Kvalifikation

Kandidatexamen, Masterexamen

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