Senior Design Lead
Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · Inbyggda system
I korthet
Ansvarsområden
- Full chip TB Architecture definition
- ASIC/SoC testplan writing
- UVM-based testbench development
- Building and maintaining reusable block-level and sub-system testbenches using SystemVerilog and UVM
- SV functional coverage and Assertions coding
- Writing, executing, and debugging constrained-random and directed test cases
- Developing TB components for SOC with C and SV
- Test case development, coding, execution, and bug analysis
- Setting up functional coverage, writing system assertions (SVA), and analyzing code coverage metrics
- Debugging complex simulation failures using waveform viewer tools
- SOC C based tests coding & debugging
- Gate level simulation & netlist debugging
- Regression failure analysis
- Functional and Code Coverage closure
- Participating in verification closure
- ATE test
Krav
- 5 to 7 years of experience is mandatory
- Good understanding of ASIC/SoC life cycle
- Participated in multiple ASIC/SoC verification till tapeout stage
- Expertise & hands-on experience in OVM/UVM methodologies using SV
- Experience in developing TB components, including functional coverage implementation and assertion coding
- Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.
- Debug complex simulation failures using waveform viewer tools to isolate design bugs from testbench issues.
- Experience in SOC C based tests coding & debugging
- Experience in Gate level simulation & netlist debugging
- Experience in regression failure analysis
- Experience in Perl/Shell scripting
- Proficiency in Verilog, SystemVerilog, and core concepts of UVM.
- Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.
- Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verdi).
- Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C, PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE).
- Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation.
Önskade kvalifikationer
- Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), VLSI Design, or a closely related field
Förmåner
- Consolidated revenues as of 12 months ending June 2026 totaled $14.8 billion.
- Global technology company, home to more than 223,000 people across 60 countries
- Delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products.
- Work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services.
Färdigheter
HCLTech is a global technology company, home to 219,000+ people across 54 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending September 2022 totaled $12.1 billion. To learn how we can supercharge progress for…
Företag
HCLTechPublicerade jobb
för 2 dagar sedan
Anställningstyp
Heltid
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Erfarenhetsnivå
Senior
Platser
Bangalore, India
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