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RTL Design - Sr Lead Engineer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

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As a Sr Lead Engineer in RTL Design at Qualcomm in Noida, India, you will be responsible for logic design, micro-architecture, RTL coding, and SoC design, synthesis, and timing analysis. This role requires extensive experience with Verilog/System-Verilog and knowledge of various protocols and ASIC development tools.

Ansvarsområden

  • Plan, design, optimize, verify, and test electronic systems, circuits, digital/analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.
  • Collaborate with cross-functional teams to develop solutions and meet performance requirements.
  • Perform logic design, micro-architecture, and RTL coding.
  • Conduct SoC design, synthesis, and timing analysis for complex SoCs.
  • Work closely with the SoC DFT, Physical Design and STA teams.
  • Design for Low power SoC.
  • Handle Multi Clock designs and Asynchronous interfaces.

Krav

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
  • OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
  • OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
  • 5 to 8 Years of Experience in Logic design /micro-architecture / RTL coding
  • Hands-on experience with SoC design, synthesis and timing analysis for complex SoCs.
  • Experience in Verilog/System-Verilog is a must.
  • Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC.
  • Hands-on experience in Low power SoC design is required.
  • Hands-on experience in Multi Clock designs, Asynchronous interface is a must.
  • Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required.
  • Experience in Synthesis / Understanding of timing concepts

Önskade kvalifikationer

  • Understanding of constraint development and timing closure is a plus.

Förmåner

  • Qualcomm is an equal opportunity employer.
  • Qualcomm is committed to providing an accessible process for individuals with disabilities.
  • Qualcomm is committed to making our workplace accessible for individuals with disabilities.
  • Reasonable accommodations will be provided to support individuals with disabilities to be ableparticipate in the hiring process.
#RTL Design#Sr Lead Engineer#Hardware Engineering#SoC Design#ASIC Development
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Företag

Qualcomm

Publicerade jobb

för 1 månad sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Noida, India

Kvalifikation

Kandidatexamen, Masterexamen, Doktorand

Sökande

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