RTL Design - Sr Engineer

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I korthet

Qualcomm is seeking an experienced Sr. RTL Design Engineer in Chennai, Tamil Nādu, India. The role involves working with AMBA protocols, SoC clocking/reset/debug architecture, memory controller designs, and low power SoC design. Experience with synthesis, timing closure, and ASIC development tools like Lint, CDC, Design Compiler, and Primetime is required.

Ansvarsområden

Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC.
Understanding of Memory controller designs and microprocessors is an added advantage.
Hands-on experience in constraint development and timing closure.
Work closely with the SoC verification and validation teams for pre/post Silicon debug.
Hands-on experience in Low power SoC design is required.
Experience in Synthesis / Understanding of timing concepts for ASIC is required.
Hands-on experience in Multi Clock designs, Asynchronous interface is a must.
Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.

Krav

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
Hands on experience in constraint development and timing closure.
Hands on experience in Low power SoC design is required.
Experience in Synthesis / Understanding of timing concepts for ASIC is required.
Hands on experience in Multi Clock designs, Asynchronous interface is a must.
Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.

Önskade kvalifikationer

Understanding of Memory controller designs and microprocessors is an added advantage.

Färdigheter

AMBAAXIAHBAPBSoC clockingSoC resetSoC debugUSBPCIESDCCMemory controllerMicroprocessorsConstraint developmentTiming closureLow power SoC designSynthesisTiming concepts for ASICMulti Clock designsAsynchronous interfaceLintCDCDesign compilerPrimetimeApplication-Specific Integrated CircuitAlgorithmsCompilersArchitecture

#RTL Design#Hardware Engineering#ASIC#SoC#AMBA#AXI#AHB#APB#USB#PCIE#SDCC#Memory controller#Microprocessors#Timing closure#Low power#Synthesis#Lint#CDC#Design compiler#Primetime#Chennai