The Job

RTL Design Engineer, Sr Lead

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · Inbyggda system

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I korthet

Qualcomm is seeking a highly motivated Senior Lead RTL Design Engineer with over 5 years of experience in front-end ASIC/SoC design. Responsibilities include micro-architecture development, RTL implementation, and quality signoff activities such as Lint and CDC analysis. Collaboration with architecture, verification, DFT, and physical design teams is essential for delivering high-quality silicon.

Ansvarsområden

  • Develop detailed micro-architecture specifications from high-level architectural requirements.
  • Design and implement synthesizable RTL using Verilog/SystemVerilog.
  • Participate in design reviews and ensure design quality and compliance with coding guidelines.
  • Perform RTL quality checks including Lint, CDC/RDC analysis and closure, and FSM and structural checks.
  • Develop and maintain design documentation including micro-architecture and interface specifications.
  • Work closely with verification teams to define verification plans and resolve functional issues.
  • Support synthesis, timing analysis, and timing closure activities.
  • Develop and review SDC constraints for block-level and subsystem-level designs.
  • Analyze and debug issues across simulation, synthesis, and implementation stages.
  • Collaborate with DFT and physical design teams for successful integration and tapeout.

Krav

  • Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
  • 5+ years of experience in ASIC/SoC front-end design.
  • Strong knowledge of digital design fundamentals.
  • Hands-on expertise in RTL design using Verilog/SystemVerilog.
  • Hands-on expertise in micro-architecture definition and documentation.
  • Hands-on expertise in Lint tools (SpyGlass, Questa Lint, or equivalent).
  • Hands-on expertise in CDC/RDC tools (SpyGlass CDC, Questa CDC, or equivalent).
  • Good understanding of clocking architectures, reset strategies, and low-power design concepts.
  • Experience debugging RTL and simulation issues.

Önskade kvalifikationer

  • Experience with synthesis flows using Design Compiler, Genus, or equivalent tools.
  • Experience creating and reviewing timing constraints (SDC).
  • Understanding of timing analysis concepts including setup/hold, clock domain crossings, and timing closure.
  • Exposure to DFT methodologies and integration.
  • Knowledge of low-power design techniques (UPF/CPF).
  • Experience with complex SoC/IP development and integration.
  • Strong analytical and debugging skills.
  • Excellent written and verbal communication.
  • Ability to work independently and drive block ownership.
  • Strong collaboration skills across architecture, verification, and physical design teams.
  • Experience working on high-performance CPU, DSP, AI/ML, networking, multimedia, or connectivity IPs.
  • Scripting knowledge in Python, Perl, or TCL for automation and flow enhancement.

Förmåner

  • Qualcomm is an equal opportunity employer.
  • Qualcomm is committed to providing an accessible process for individuals with disabilities.
  • Qualcomm is committed to making our workplace accessible for individuals with disabilities.
#RTL Design#ASIC#SoC#Hardware Engineering#Verilog#SystemVerilog
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Företag

Qualcomm

Publicerade jobb

för 3 veckor sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Bangalore, India

Kvalifikation

Kandidatexamen, Masterexamen, Doktorand

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