R&D Engineering, Staff Engineer - Design Verification/ VIP Verification Engineers
Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · QA och testning
I korthet
Synopsys is looking for a Staff Engineer to join their R&D team in Delhi, India. The role focuses on designing, developing, and maintaining Verification IP (VIP) using SystemVerilog and UVM for industry-standard protocols. The ideal candidate will have a strong understanding of verification methodologies and a passion for ensuring the quality and reliability of semiconductor designs.
Ansvarsområden
- Design, develop, and maintain Verification IP using SystemVerilog and UVM for industry-standard protocols including DFI, DRAM, AMBA, PCIe, USB, and Ethernet
- Build comprehensive verification plans that map protocol specifications to testable scenarios, coverage goals, and corner case strategies
- Code sequences, test scenarios, and checkers that drive coverage-based verification across functional and code coverage dimensions
- Debug complex simulation failures across multi-layer protocol stacks, identifying root causes in both VIP logic and customer integration environments
- Enhance existing VIP products for performance, reusability, and scalability as protocols evolve and customer use cases expand
- Support customers during VIP integration and deployment, troubleshooting issues, answering technical questions, and ensuring successful bring-up
- Collaborate with Design IP teams, R&D engineers, and field application teams to align VIP capabilities with product roadmaps and customer needs
Krav
- Bachelor's or Master's degree in Electronics Engineering, Computer Science, or equivalent practical experience
- 5+ years of hands-on experience developing Verification IP or SystemVerilog/UVM-based test benches
- Deep working knowledge of at least two industry-standard protocols such as AMBA (AXI, AHB, APB), DFI, DRAM, PCIe, or Ethernet
- Strong proficiency in SystemVerilog and UVM methodology for building reusable, scalable verification environments
- Demonstrated ability to create and execute coverage-driven verification plans, including functional and code coverage analysis
- Experience debugging complex simulation failures and resolving issues across protocol layers and integration boundaries
- Experience working directly with customers or field teams during product deployment is a strong plus
Önskade kvalifikationer
- Translate protocol specifications into verification plans covering corner cases
- Debug failing sequences across large log outputs
- Possess strong opinions about VIP architecture and push back on shortcuts
- Find working with customers during integration a natural extension of work
- Manage multiple VIP enhancements, customer issues, and verification plans in parallel
- Own the final 10% of tasks, validating outcomes, tightening documentation, and ensuring complete, high-quality delivery
Förmåner
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Retirement plans that vary by region and country
- Competitive salaries
#R&D#Engineering#Design Verification#VIP Verification#Staff Engineer
Företag
Synopsys Inc
Publicerade jobb
för 2 dagar sedan
Anställningstyp
Heltid
Arbetsform
På plats
Erfarenhetsnivå
Senior
Platser
Delhi, India
Kvalifikation
Kandidatexamen, Masterexamen
Sökande
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