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R&D Engineering, Sr Staff Engineer

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I korthet

Synopsys is seeking a Senior Staff Engineer for R&D Engineering in Hyderabad, India. This role involves designing and developing CMOS embedded memories, with a focus on optimizing speed, power, and density. The ideal candidate has 8+ years of hands-on CMOS memory design experience, including production tapeout and lab bring-up.

Ansvarsområden

  • Design and develop CMOS embedded memories including SP SRAM, DP SRAM, Register Files, and ROM across ultra high speed, ultra low power, and high density design portfolios
  • Own architecture definition and circuit implementation for memory compilers, making the critical tradeoffs that determine performance, area, and yield
  • Perform schematic entry, circuit simulation using SPICE-based tools, layout planning, and supervise physical layout teams through design closure
  • Develop and verify bit cells from initial topology exploration through full layout verification, including parasitic extraction and post-layout simulation
  • Interface directly with CAD teams to automate memory compiler flows and with frontend engineers to generate EDA models and enable full verification integration
  • Debug and resolve design issues across the full stack, from transistor-level failures to compiler automation bugs
  • Lead and mentor junior engineers and trainees on memory design methodology, circuit techniques, and verification best practices

Krav

  • Bachelor's or Master's degree in Electrical Engineering, Electronics, Telecommunications, or a related technical field
  • 8+ years of hands-on CMOS memory design experience with production tapeout responsibility
  • Deep proficiency in memory circuit design, SPICE simulation, layout planning, parasitic extraction, and layout verification tools
  • Strong scripting capability in C-Shell and Perl; experience with C++ or JavaScript is a plus
  • Demonstrated experience developing bit cells and driving physical layout design through to verification closure
  • Experience interfacing with memory compiler automation flows and EDA model generation
  • Proven ability to lead technical projects and mentor junior engineers through complex design challenges

Önskade kvalifikationer

  • You can look at a memory timing diagram and immediately identify whether the access time claim is real or whether someone is hiding margin
  • When a layout comes back with LVS errors, you do not wait for the layout team to figure it out, you open the GDS yourself and find the short
  • You write documentation and design reviews that actually help people understand the decisions you made, not just what you built
  • You are comfortable presenting a circuit tradeoff to a senior architect and defending your approach with data, not intuition
  • You know when to push back on a spec that cannot be met and when to find a creative way to make it work
  • You stay current on memory design techniques and process technology trends because you care about building better circuits, not just finishing tasks

Förmåner

  • Comprehensive medical and healthcare plans that work for you and your family.
  • In addition to company holidays, we have ETO and FTO Programs.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
  • Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
  • Save for your future with our retirement plans that vary by region and country.
  • Competitive salaries.
#R&D#Engineering#CMOS memory design#SRAM#circuit design#layout#simulation#verification#chip design#AI/ML#GenAI#Cloud
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Företag

Synopsys Inc

Publicerade jobb

för 1 månad sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Hyderabad, India

Kvalifikation

Kandidatexamen, Masterexamen

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