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R&D Engineering, Sr Manager

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

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Synopsys is looking for an experienced R&D Engineering Sr. Manager in Noida, India, to lead a team focused on developing advanced embedded memory IP across various architectures and nodes. The role requires extensive experience in memory design, circuit implementation, team leadership, and project management, with a focus on low-power and area-efficient solutions.

Ansvarsområden

  • Lead a team of engineers developing SRAM, Register File, TCAM, and ROM architectures and circuit implementations across advanced FinFET nodes.
  • Oversee the full memory design flow from architecture definition through schematic entry, simulation, layout planning, verification, characterization, and model generation.
  • Drive low-power and area-efficient circuit design strategies, balancing performance, variation, and manufacturability constraints.
  • Coordinate with CAD teams on layout verification, parasitic extraction, and compiler automation using Perl and Python.
  • Manage project timelines, prioritize deliverables, and resolve technical and resourcing issues across multi-site teams.
  • Build and maintain relationships with internal stakeholders and external customers, translating technical requirements into executable design plans.
  • Mentor engineers on memory compiler development, transistor-level design, and advanced node challenges.

Krav

  • BE/B.Tech/ME/M.Tech/MS in Electrical & Electronics Engineering from a recognized institute or university.
  • 15+ years of hands-on experience in embedded memory design, including SRAM, Register File, TCAM, or ROM.
  • Deep expertise across the full memory design flow: architecture, circuit design, layout, compiler automation, characterization, timing, and model generation.
  • Proven experience leading engineering teams and delivering complex projects on schedule in a multi-site environment.
  • Strong proficiency in Perl and Python for design automation and scripting.
  • Hands-on experience with deep submicron and FinFET technologies, including variation-aware design techniques.
  • Solid understanding of CMOS fundamentals, digital design, RC circuits, transfer function analysis, and CMOS fabrication processes.

Önskade kvalifikationer

  • Ability to identify and resolve complex technical issues, such as timing violations, during layout reviews.
  • Skill in managing multiple projects and shifting priorities while effectively communicating risks and tradeoffs.
  • Proven ability to build trust across teams through follow-through and recognition.
  • Capacity to handle difficult conversations about design specifications early enough to allow for options.
  • Mentorship style focused on guiding engineers through problem-solving.
  • Up-to-date knowledge of memory design trends, advanced node challenges, and industry best practices.

Förmåner

  • Comprehensive medical and healthcare plans.
  • ETO and FTO Programs.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
  • ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
  • Retirement Plans.
  • Competitive salaries.
#engineering#R&D#EDA#chip design#verification#manufacturing#embedded memory#SRAM#Register File#TCAM#ROM#FinFET#low-power design#circuit design#automation
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Företag

Synopsys Inc

Publicerade jobb

för 2 veckor sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Noida, India

Kvalifikation

Kandidatexamen, Masterexamen

Sökande

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