The Job

Physical Design , Principal Engineer/Director, (Custom Silicon Group)

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I korthet

Qualcomm seeks an ASIC Design Manager (Principal/Director-Level) in Bangalore to lead the development of next-generation high-performance SoCs. This role involves managing engineering teams, driving the complete silicon development lifecycle, and acting as a key customer-facing leader to translate requirements into silicon solutions.

Ansvarsområden

  • Lead and manage a team across multiple functions and sites.
  • Drive PnR implementation including Floor planning, Placement, CTS, and post-route activities on cutting-edge nodes.
  • Ensure design closure and tapeout expertise in advanced technology nodes.
  • Provide mandatory signoff knowledge, including STA, Power Analysis, FV, Low Power Verification and PV.
  • Collaborate to resolve issues related to constraints validation, verification, STA, Physical Design and tapeout.
  • Understand deep sub-micron design challenges, including leakage power, signal integrity, and DFM.
  • Support pre-sales and business development activities by evaluating technical feasibility and providing design expertise.
  • Provide technical leadership during design reviews and executive-level customer engagements.
  • Drive resolution of customer-reported issues by coordinating across design, verification, firmware, software, and validation teams.

Krav

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.
  • Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.
  • PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
  • Bachelor's or Master’s degree in Electrical/Electronics Engineering and 17- 25 years of Hardware/VLSI Engineering specializing in Physical Design and timing signoff for high-speed SoCs.

Önskade kvalifikationer

  • Excellent hands-on experience on Floor planning, PnR and STA flows.
  • Good knowledge of Placement/Clock Tree Synthesis (CTS), Low Power/High Performance optimization etc.
  • Thorough understanding of signoff domains– LEC/CLP/PDN etc.
  • 18+ years of experience with Physical Design and timing signoff expertise in latest tech nodes (e.g., 2nm/3nm/4nm/5nm).
#Hardware Engineering#ASIC Design#Silicon Development#SoC Design#Physical Design#Timing Signoff
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Företag

Qualcomm

Publicerade jobb

för 1 månad sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Ledning

Platser

Bangalore, India

Kvalifikation

Kandidatexamen, Masterexamen, Doktorand

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