The Job

Physical Design, Principal Engineer

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I korthet

Synopsys seeks a Principal ASIC Physical Design Engineer in Bengaluru, India to drive physical design for advanced nodes (7nm and below) using tools like ICC2 and PrimeTime. The role involves timing closure, clock tree synthesis, mixed-signal integration, and mentoring junior engineers, with a focus on delivering high-performance IP for consumer and enterprise devices.

Ansvarsområden

  • Implement and integrate Physical Design for ASICs at advanced nodes (10nm, 7nm, 6nm and below) using tools like Synopsys ICC2, PrimeTime, and StarRC.
  • Drive timing closure for high-frequency designs above 4GHz, handling constraint management, analysis, and optimization.
  • Work hands-on with clock tree synthesis, skew balancing, and robust clock distribution for complex SoCs and IPs.
  • Collaborate closely with teams in Bangalore and the US, joining technical discussions, design reviews, and troubleshooting sessions.
  • Integrate mixed-signal hard macro IPs, solving unique interface and floorplan challenges as they arise.
  • Mentor junior engineers, sharing best practices and elevating the team’s technical capability.
  • Develop and optimize automation scripts in Tcl, Perl, or Python to streamline physical design flows and improve productivity.
  • Support and improve methodologies for floorplanning, placement, routing, and power optimization.

Krav

  • Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or related field.
  • 10+ years of hands-on experience in ASIC physical design at 10nm, 7nm, 6nm or below.
  • Deep proficiency with Synopsys ICC2, PrimeTime, StarRC, and similar industry tools.
  • Demonstrated success in timing closure for high-frequency designs (4GHz and above), including constraint management and analysis.
  • Practical experience integrating HPC Controller interface IPs and mixed-signal macros.
  • Solid knowledge of scripting (Tcl, Perl, Python) for automating physical design tasks.
  • Strong skills in debugging complex design and integration issues.

Önskade kvalifikationer

  • You explain why a timing violation matters, not just how to fix it, and adapt your message for a peer or a VP.
  • When a design review gets stuck, you break down the complexity and help the team move forward.
  • You spot risk early and act, rather than waiting for issues to escalate.
  • Sharing knowledge is second nature—you mentor, document, and help others level up.
  • You keep an eye on quality, even under pressure, and push for continuous improvement in tools and process.
  • You are comfortable switching context between deep technical work and cross-site collaboration, always keeping the larger goal in view.

Förmåner

  • Comprehensive medical and healthcare plans.
  • ETO and FTO Programs for time away.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
  • ESPP to purchase Synopsys common stock at a 15% discount.
  • Retirement plans.
  • Competitive salaries.
#ASIC#Physical Design#Engineering#Chip Architecture#Circuit Design#Verification#Semiconductor#HPC Controller IPs#Mixed-signal Integration#Timing Closure#Clock Tree Synthesis
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Företag

Synopsys Inc

Publicerade jobb

för 6 dagar sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Bengaluru, India

Kvalifikation

Kandidatexamen, Masterexamen

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