The Job

Physical Design (Multiple levels)

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Qualcomm is seeking Physical Design Engineers for its SoC and ASIC Design organization in San Diego, CA. This role involves contributing to various projects, including high-performance computing, AI, mobile, automotive, and data center technologies, utilizing advanced process technologies and collaborating with world-class teams.

Ansvarsområden

  • Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
  • Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
  • Perform floorplanning, partitioning, power planning, and IR-drop analysis.
  • Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios.
  • Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
  • Perform RC extraction, physical verification, and formal verification activities.
  • Implement engineering change orders (ECOs) and support design convergence through sign-off.
  • Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution.
  • Contribute to the development of innovative low-power implementation methodologies and customized place-and-route solutions.
  • Develop automation and productivity tools using scripting languages and software development techniques.

Krav

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
  • 2-10+ years of industry experience or relevant academic/project experience in Physical Design.

Önskade kvalifikationer

  • Experience in ASIC/SoC Physical Design implementation.
  • Experience with Place and Route using Cadence Innovus and/or Synopsys Fusion Compiler.
  • Experience with Static Timing Analysis and timing closure using Synopsys PrimeTime SI.
  • Experience with physical verification and design sign-off methodologies.
  • Experience with formal verification techniques and tools.
  • Experience with power domain implementation and low-power design methodologies.
  • Experience with Clock Tree Synthesis (CTS), routing, and timing optimization.
  • Low power implementation techniques experience.
  • Experience with signal integrity, noise analysis, and MMMC sign-off flows.
  • DFT-aware physical implementation and constraint management.
  • Programming and automation using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments.
  • Perl/Tcl, Python skills are needed.
  • Strong problem solving and ASIC development/debugging skills.

Förmåner

  • Competitive annual discretionary bonus program.
  • Opportunity for annual RSU grants.
  • Highly competitive benefits package designed to support your success at work, at home, and at play.
  • The ability to work on leading-edge products on advanced process technologies.
#ASIC#SoC#Physical Design#Floorplan#Clock Tree Synthesis#Low Power#Timing Analysis#Tape-out#Placement#Routing#Timing Closure#RC Extraction#Physical Verification#Formal Verification#ECO#DFT#Scripting#Python#Perl#TCL#Shell#C++#Linux#Unix
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Företag

Qualcomm

Publicerade jobb

för 3 veckor sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Mellannivå

Platser

San Diego, United States of America

Kvalifikation

Kandidatexamen, Masterexamen, Doktorand

Sökande

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