Physical Design Engineer, Senior Lead

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

I korthet

Qualcomm is seeking a Senior Lead Physical Design Engineer to join their Hardware Engineering group in Hyderabad, India. The role involves planning, designing, and verifying ASIC physical designs, including Place and Route, timing closure, and sign-off checks, utilizing tools like Innovus and Fusion Compiler, and scripting languages.

Ansvarsområden

Plan, design, optimize, verify, and test electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.
Collaborate with cross-functional teams to develop solutions and meet performance requirements.
Execute complete PD ownership from netlist to GDS2 including HM level PV, LEC, low-power checks and PDN, STA closure.
Implement Voltage Islands and low power methodologies, flows and implementation.
Debug Congestion and CTS issues.
Perform PnR with tools like Innovus/Fusion compiler and flow.
Familiarize with Sign-off methodology and tools (PV/PDN/STA/FV/CLP/Scan-DRC(tk)).
Understand and implement improving existing methodologies and flows.
Effectively communicate the status and issues of respective owned Tasks.
Work in a global team environment.

Krav

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
Thorough knowledge of the ASIC designs Place and Route flow and methodology.
Hands-on experience in executing complete PD ownership from netlist to GDS2 including HM level PV, LEC, low-power checks and PDN, STA closure.
Hands-on experience in Voltage Islands and low power methodologies, flows and implementation.
Strong background in debugging Congestion and CTS issues.
Expertise in PnR tools (Innovus/Fusion compiler) and flow.
Familiarity with Sign-off(PV/PDN/STA/FV/CLP/Scan-DRC(tk)) methodology and tools.
Proficient in scripting languages (TCL,PERL,PYTHON).
4-10 yrs of experience in physical design including floorplanning, PNR, CTS and signoff checks.

Önskade kvalifikationer

Self-starter and highly motivated
To have working experience in global team environment.
To be effectively communicate the status and issues of respective owned Tasks.

Förmåner

Qualcomm is an equal opportunity employer.
Qualcomm is committed to providing an accessible process for individuals with disabilities.
Qualcomm is committed to making our workplace accessible for individuals with disabilities.

Färdigheter

TCLPERLPYTHONASIC DesignPlace and RouteLEClow-powerPDNSTAVoltage IslandsCongestionCTSPnRInnovusFusion compilerSign-offPVFVCLPScan-DRCtk

#Hardware Engineering#ASIC#Physical Design#Place and Route#GDS2#PV#LEC#low-power#PDN#STA#Voltage Islands#Congestion#CTS#Innovus#Fusion compiler#Sign-off#FV#CLP#Scan-DRC#tk#TCL#PERL#PYTHON