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NOC Design - Sr Engineer

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I korthet

The Sr Engineer, NOC Design will be responsible for the verification of next-generation Infrastructure IPs for System-on-Chip (SoC) at Qualcomm. This role involves planning and implementing IP/Cluster/Formal verification flows, coordinating with cross-functional teams, and ensuring quality sign-off for cutting-edge products.

Ansvarsområden

  • Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage)
  • Develop test plan and test cases to cover design feature set, follow up with stakeholders on code coverage, functional coverage closure at different levels of test bench
  • Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure
  • Debug of regression signatures and identifying bug fixes
  • Responsible for Quality sign off and required documentation
  • Developing/Deploying scripts/tools for validation (Certitude, VC Formal, VPlan)
  • Debug and root cause post silicon issues in collaboration with Design, SW and test teams
  • Work with SoC level performance modeling team on latency, bandwidth analysis

Krav

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
  • Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
  • PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
  • Strong debugging, Analytical and problem-solving skills
  • Expertise on UVM based verification
  • Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture
  • Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved
  • Communication and collaboration skills to work with a large world-wide design organization
  • 8 Years of Experience in IP verification or related
  • Experience with UVM and ARM Bus protocols.

Önskade kvalifikationer

  • Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse
  • Experience in verifying designs meeting Automotive Safety Integrity Levels (ASIL)
  • Proficiency in Scripting languages (Python or Perl) for Automation initiatives, C/C++/SystemC for performance models
  • Post-si bring-up and HW-SW debug experience would be a plus.
  • Knowledge & exposure to silicon debug tool chains would be an added advantage
#NOC Design#Sr Engineer#Hardware Engineering#Verification Architect#IP verification#System-on-chip#SoC#UVM#ARM bus protocols#Python#Perl#C++#SystemC
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Företag

Qualcomm

Publicerade jobb

för 3 dagar sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Bangalore, India

Kvalifikation

Kandidatexamen, Masterexamen, Doktorand

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