Next-Gen, High-Speed HBM, LPDDR Memory Controller ASIC Digital Design Engineer

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I korthet

Qualcomm is looking for a Senior ASIC Design Engineer to join their Next Generation, High-Speed Memory and Cache Controller Design Team. The role involves architecture, RTL coding, and deployment of high-speed memory systems (1Ghz+) into QCT products, with responsibilities including specification development, micro-architecture, RTL implementation, debugging, and contributing to design methodology improvements.

Ansvarsområden

Develop architecture and design specifications for next generation, high-speed memory systems.
Drive the micro-architecture of portions of the logic design.
Implement and deliver RTL.
Work with verification engineers to deliver high quality designs.
Debug designs and provide debug support during chip integration.
Perform Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, and Power Analysis.
Contribute to the improvement of design methodology to drive productivity and quality.

Krav

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
5+ years ASIC design, RTL coding, front-end digital design experience.
3+ years Hardware Architecture experience.
Master's degree in Computer Engineering and/or Electrical Engineering.

Önskade kvalifikationer

Bachelors or Masters degree in Science, Engineering, or related field.
3-10 years of ASIC design (RTL coding) Preferred.
Exposure to RTL Design Verification flows is a plus.
3+ years of direct Hardware Architecture experience.
Bachelors degree in Electrical or Computer Engineering and at least 5+ years of experience in high speed digital design (Master's degree preferred).
Experience with LPDDR memory and cache controller, NoC based architectures especially the front end interfacing to the CPU, DSP, and multimedia processors.
Exposure to HBM memory type designs.
On-chip tightly coupled SRAM & L3 cache controller architecture/design.
Experience with x86 or ARM CPU/bus architectures.
Experience with ordering of memory transactions and methods to enforce proper ordering in order to conform to ISA architecture specification.

Förmåner

Competitive annual discretionary bonus program.
Opportunity for annual RSU grants.
Highly competitive benefits package designed to support success at work, at home, and at play.
Will discuss all that Qualcomm has to offer.

#ASIC#HBM#LPDDR#Memory Controller#Digital Design#Engineer

Företag

Qualcomm

Publicerade jobb

för 2 dagar sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

San Diego, United States of America

Kvalifikation

Masterexamen, Kandidatexamen, Doktorand

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